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author | Kevin Lim <ktlim@umich.edu> | 2007-03-23 13:20:19 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2007-03-23 13:20:19 -0400 |
commit | 047f77102b5e5d63549663ee94cd799cdcf63516 (patch) | |
tree | 3c214a93043533716044b1c61c9d12aba3388c42 /src/mem/cache/cache_impl.hh | |
parent | 2c47413a7a4563c724d8470971d1059bdfe01c92 (diff) | |
parent | 2330adfa28ec39035beab8dae52873ecd0e28889 (diff) | |
download | gem5-047f77102b5e5d63549663ee94cd799cdcf63516.tar.xz |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
--HG--
extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r-- | src/mem/cache/cache_impl.hh | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 5c6ab0950..fc4660269 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -545,8 +545,13 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt) //We are determining prefetches on access stream, call prefetcher prefetcher->handleMiss(pkt, curTick); } + + Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); + if (!pkt->req->isUncacheable()) { - blk = handleAccess(pkt, lat, writebacks); + if (!missQueue->findMSHR(blk_addr)) { + blk = handleAccess(pkt, lat, writebacks); + } } else { size = pkt->getSize(); } |