First pass, now compiles with current head of tree.

Compile and initialization work, still working on functionality.

src/mem/cache/base_cache.cc:
    Temp fix for cpu's use of getPort functionality.  CPU's will need to be ported to the new connector objects.
    Also, all packets have to have data or the delete fails.
src/mem/cache/cache.hh:
    Fix function prototypes so overloading works
src/mem/cache/cache_impl.hh:
    fix functions to match virtual base class
src/mem/cache/miss/miss_queue.cc:
    Packets havve to have data, or delete fails
src/python/m5/objects/BaseCache.py:
    Update for newmem

--HG--
extra : convert_revision : 2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb

1 files changed, 4 insertions, 4 deletions

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index f1e9c3698..0cb33461b 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -77,7 +77,7 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
 template<class TagStore, class Buffering, class Coherence>
 Tick
 Cache<TagStore,Buffering,Coherence>::
-doAtomicAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+doAtomicAccess(Packet *pkt, bool isCpuSide)
 {
     if (isCpuSide)
     {
@@ -97,18 +97,18 @@ doAtomicAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
 template<class TagStore, class Buffering, class Coherence>
 void
 Cache<TagStore,Buffering,Coherence>::
-doFunctionalAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+doFunctionalAccess(Packet *pkt, bool isCpuSide)
 {
     if (isCpuSide)
     {
-        probe(pkt, false);
+        probe(pkt, true);
     }
     else
     {
         if (pkt->isResponse())
             handleResponse(pkt);
         else
-            snoopProbe(pkt, false);
+            snoopProbe(pkt, true);
     }
 }