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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:57 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:57 -0400 |
commit | 072a91ee51032a2985783d4a17dca6e918ad3023 (patch) | |
tree | 79403df95bb85711a1ed193cfdd251bb1bb9934b /src/mem/cache/cache_impl.hh | |
parent | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (diff) | |
download | gem5-072a91ee51032a2985783d4a17dca6e918ad3023.tar.xz |
Configs: Set the memtest clock to a reasonable value
This patch changes the memtest clock from 1THz (the default) to 2GHz,
similar to the CPUs in the other regressions. This is useful as the
caches will adopt the same clock as the CPU. The bus clock rate is
scaled accordingly, and the L1-L2 bus is kept at the CPU clock while
the memory bus is at half that frequency.
A separate patch updates the affected stats.
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
0 files changed, 0 insertions, 0 deletions