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authorSteve Reinhardt <stever@eecs.umich.edu>2006-10-18 08:16:22 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2006-10-18 08:16:22 -0700
commit6cd187e1f066b084740b4b202f1de644ba06f299 (patch)
tree32db5b9458ccf1d39669b94693baff56afbb47d2 /src/mem/cache/cache_impl.hh
parent0128b73d0588ecdf66fcb482fddad2853216edce (diff)
downloadgem5-6cd187e1f066b084740b4b202f1de644ba06f299.tar.xz
Get rid of obsolete in-cache copy support.
--HG-- extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r--src/mem/cache/cache_impl.hh38
1 files changed, 0 insertions, 38 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 44d7b4895..9504d16c6 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -148,7 +148,6 @@ Cache(const std::string &_name,
prefetchAccess(params.prefetchAccess),
tags(params.tags), missQueue(params.missQueue),
coherence(params.coherence), prefetcher(params.prefetcher),
- doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
hitLatency(params.hitLatency)
{
tags->setCache(this);
@@ -350,43 +349,6 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
}
template<class TagStore, class Buffering, class Coherence>
-void
-Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
-{
- // Need to temporarily move this blk into MSHRs
- MSHR *mshr = missQueue->allocateTargetList(addr);
- int lat;
- PacketList dummy;
- // Read the data into the mshr
- BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
- assert(dummy.empty());
- assert(mshr->pkt->flags & SATISFIED);
- // can overload order since it isn't used on non pending blocks
- mshr->order = blk->status;
- // temporarily remove the block from the cache.
- tags->invalidateBlk(addr);
-}
-
-template<class TagStore, class Buffering, class Coherence>
-void
-Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
-{
- // Need to temporarily move this blk into MSHRs
- assert(mshr->pkt->cmd == Packet::ReadReq);
- int lat;
- PacketList dummy;
- // Read the data into the mshr
- BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
- assert(dummy.empty());
- assert(mshr->pkt->flags & SATISFIED);
- // can overload order since it isn't used on non pending blocks
- mshr->order = blk->status;
- // temporarily remove the block from the cache.
- tags->invalidateBlk(mshr->pkt->getAddr());
-}
-
-
-template<class TagStore, class Buffering, class Coherence>
Packet *
Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
{