Fix for DMA's in FS caches.

Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)

Now both timing/atomic caches with MOESI in UP fail at same point.

src/dev/io_device.hh:
    DMA's should send WriteInvalidates
src/mem/bridge.cc:
    Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Fix CSHR's for flow control.
src/mem/packet.hh:
    Make a writeInvalidateResp, since the DMA expects responses to it's writes

--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd

1 files changed, 10 insertions, 0 deletions

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 9db79b843..00f93328e 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -304,6 +304,7 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 {
     BlkType *blk = NULL;
     if (pkt->senderState) {
+        ((MSHR*)pkt->senderState)->pkt = pkt;
         if (pkt->result == Packet::Nacked) {
             //pkt->reinitFromRequest();
             warn("NACKs from devices not connected to the same bus not implemented\n");
@@ -379,6 +380,15 @@ Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
     return coherence->getPacket();
 }
 
+template<class TagStore, class Buffering, class Coherence>
+void
+Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
+                                                         MSHR *cshr,
+                                                         bool success)
+{
+    coherence->sendResult(pkt, cshr, success);
+}
+
 
 template<class TagStore, class Buffering, class Coherence>
 void