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authorPrakash Ramrakhyani <prakash.ramrakhyani@arm.com>2013-06-27 05:49:50 -0400
committerPrakash Ramrakhyani <prakash.ramrakhyani@arm.com>2013-06-27 05:49:50 -0400
commitac515d7a9b131ffc9e128bd209fcddb2f383808b (patch)
tree4a445dffeed869dac321abc09b04d7c3d65601fe /src/mem/cache/cache_impl.hh
parent0d68d36b9d12c36e6201fa8bc4bec34258c04eab (diff)
downloadgem5-ac515d7a9b131ffc9e128bd209fcddb2f383808b.tar.xz
mem: Reorganize cache tags and make them a SimObject
This patch reorganizes the cache tags to allow more flexibility to implement new replacement policies. The base tags class is now a clocked object so that derived classes can use a clock if they need one. Also having deriving from SimObject allows specialized Tag classes to be swapped in/out in .py files. The cache set is now templatized to allow it to contain customized cache blocks with additional informaiton. This involved moving code to the .hh file and removing cacheset.cc. The statistics belonging to the cache tags are now including ".tags" in their name. Hence, the stats need an update to reflect the change in naming.
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r--src/mem/cache/cache_impl.hh11
1 files changed, 4 insertions, 7 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 7098dbfd3..90020c295 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -63,9 +63,9 @@
#include "sim/sim_exit.hh"
template<class TagStore>
-Cache<TagStore>::Cache(const Params *p, TagStore *tags)
+Cache<TagStore>::Cache(const Params *p)
: BaseCache(p),
- tags(tags),
+ tags(dynamic_cast<TagStore*>(p->tags)),
prefetcher(p->prefetcher),
doFastWrites(true),
prefetchOnAccess(p->prefetch_on_access)
@@ -88,7 +88,6 @@ void
Cache<TagStore>::regStats()
{
BaseCache::regStats();
- tags->regStats(name());
}
template<class TagStore>
@@ -322,8 +321,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
incMissCount(pkt);
return false;
}
- int master_id = pkt->req->masterId();
- tags->insertBlock(pkt->getAddr(), blk, master_id);
+ tags->insertBlock(pkt, blk);
blk->status = BlkValid | BlkReadable;
}
std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
@@ -1219,8 +1217,7 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
tempBlock->tag = tags->extractTag(addr);
DPRINTF(Cache, "using temp block for %x\n", addr);
} else {
- int id = pkt->req->masterId();
- tags->insertBlock(pkt->getAddr(), blk, id);
+ tags->insertBlock(pkt, blk);
}
// we should never be overwriting a valid block