Fix problems with unCacheable addresses in timing-coherence

src/base/traceflags.py:
src/mem/physical.cc:
    Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
    Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
    Set the size properly on unCacheable accesses

--HG--
extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16

1 files changed, 5 insertions, 0 deletions

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a68418f24..150abbe52 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -389,6 +389,11 @@ template<class TagStore, class Buffering, class Coherence>
 void
 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 {
+    if (pkt->req->isUncacheable()) {
+        //Can't get a hit on an uncacheable address
+        //Revisit this for multi level coherence
+        return;
+    }
     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
     BlkType *blk = tags->findBlock(pkt);
     MSHR *mshr = missQueue->findMSHR(blk_addr);