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authorRon Dreslinski <rdreslin@umich.edu>2006-11-10 22:45:50 -0500
committerRon Dreslinski <rdreslin@umich.edu>2006-11-10 22:45:50 -0500
commitf876bc2bf0e04b888c2748c0cabf8d11b31f41b7 (patch)
tree8dcd8a817d203442fdcbc332d7fed0d5ab8f8701 /src/mem/cache/cache_impl.hh
parent9a6e896d3bc904745f090aad1a6d40f04f5ac2ef (diff)
downloadgem5-f876bc2bf0e04b888c2748c0cabf8d11b31f41b7.tar.xz
More fixes for functional accesses. It now makes the writeback memory leak to crash all configs.
Working on that now. src/mem/cache/base_cache.cc: Keep a list of the responders so we can search them on functional accesses. src/mem/cache/base_cache.hh: Properly put things on a list for responses so we can search the list. Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there) src/mem/cache/cache_impl.hh: Properly return when the first read hit on a functional access. Make sure to call to check the other ports list of packets before forwarding it out. --HG-- extra : convert_revision : 1d21cb55ff29c15716617efc48441329707c088a
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r--src/mem/cache/cache_impl.hh21
1 files changed, 12 insertions, 9 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 9bb72e85c..176d9159a 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -536,7 +536,7 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
if (!update && (pkt->isWrite() || (otherSidePort == cpuSidePort))) {
// Still need to change data in all locations.
- otherSidePort->sendFunctional(pkt);
+ otherSidePort->checkAndSendFunctional(pkt);
if (pkt->isRead() && pkt->result == Packet::Success)
return 0;
}
@@ -560,30 +560,33 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
missQueue->findWrites(blk_addr, writes);
if (!update) {
+ bool notDone = !(pkt->flags & SATISFIED); //Hit in cache (was a block)
// Check for data in MSHR and writebuffer.
if (mshr) {
MSHR::TargetList *targets = mshr->getTargetList();
MSHR::TargetList::iterator i = targets->begin();
MSHR::TargetList::iterator end = targets->end();
- for (; i != end; ++i) {
+ for (; i != end && notDone; ++i) {
PacketPtr target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->intersect(pkt)) {
- fixPacket(pkt, target);
+ DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a MSHR\n",
+ blk_addr);
+ notDone = fixPacket(pkt, target);
}
}
}
- for (int i = 0; i < writes.size(); ++i) {
+ for (int i = 0; i < writes.size() && notDone; ++i) {
PacketPtr write = writes[i]->pkt;
if (write->intersect(pkt)) {
- fixPacket(pkt, write);
+ DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a writeback\n",
+ pkt->cmdString(), blk_addr);
+ notDone = fixPacket(pkt, write);
}
}
- if (pkt->isRead()
- && pkt->result != Packet::Success
- && otherSidePort == memSidePort) {
- otherSidePort->sendFunctional(pkt);
+ if (notDone && otherSidePort == memSidePort) {
+ otherSidePort->checkAndSendFunctional(pkt);
assert(pkt->result == Packet::Success);
}
return 0;