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author | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-23 09:34:22 -0800 |
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committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-23 09:34:22 -0800 |
commit | 1d3228481f3c5f9a4ad041cd21d57139f5f8f331 (patch) | |
tree | 7006a0d99e1f278df5ff88b70c4940230fe9e768 /src/mem/cache/cache_impl.hh | |
parent | be4cf50c5a6a5761f6474fb9f85a9c241101f3ce (diff) | |
download | gem5-1d3228481f3c5f9a4ad041cd21d57139f5f8f331.tar.xz |
cache: Make caches sharing aware and add occupancy stats.
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r-- | src/mem/cache/cache_impl.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 2397a17c5..206361f88 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -277,7 +277,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, if (pkt->needsExclusive() ? blk->isWritable() : blk->isReadable()) { // OK to satisfy access - hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++; + incHitCount(pkt, id); satisfyCpuSideRequest(pkt, blk); return true; } @@ -297,7 +297,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, if (blk == NULL) { // no replaceable block available, give up. // writeback will be forwarded to next level. - incMissCount(pkt); + incMissCount(pkt, id); return false; } int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; @@ -308,11 +308,11 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, blk->status |= BlkDirty; // nothing else to do; writeback doesn't expect response assert(!pkt->needsResponse()); - hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++; + incHitCount(pkt, id); return true; } - incMissCount(pkt); + incMissCount(pkt, id); if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { // complete miss on store conditional... just give up now |