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authorSteve Reinhardt <steve.reinhardt@amd.com>2009-09-26 10:50:50 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2009-09-26 10:50:50 -0700
commit72cfed41641bbea2ea3dc78958ed3b1e2c27bbf9 (patch)
treeae19cd225081c4b4f63e15e6a54d493e8ce3ccaf /src/mem/cache/cache_impl.hh
parentf28ea7a6c9ea9506524adff0f468d6dd789c510c (diff)
downloadgem5-72cfed41641bbea2ea3dc78958ed3b1e2c27bbf9.tar.xz
Force prefetches to check cache and MSHRs immediately prior to issue.
This prevents redundant prefetches from being issued, solving the occasional 'needsExclusive && !blk->isWritable()' assertion failure in cache_impl.hh that several people have run into. Eliminates "prefetch_cache_check_push" flag, neither setting of which really solved the problem.
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r--src/mem/cache/cache_impl.hh13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 80b7c545c..d8630c1f5 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1301,11 +1301,14 @@ Cache<TagStore>::getNextMSHR()
// If we have a miss queue slot, we can try a prefetch
PacketPtr pkt = prefetcher->getPacket();
if (pkt) {
- // Update statistic on number of prefetches issued
- // (hwpf_mshr_misses)
- mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
- // Don't request bus, since we already have it
- return allocateMissBuffer(pkt, curTick, false);
+ Addr pf_addr = blockAlign(pkt->getAddr());
+ if (!tags->findBlock(pf_addr) && !mshrQueue.findMatch(pf_addr)) {
+ // Update statistic on number of prefetches issued
+ // (hwpf_mshr_misses)
+ mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
+ // Don't request bus, since we already have it
+ return allocateMissBuffer(pkt, curTick, false);
+ }
}
}