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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-12 13:22:36 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-12 13:22:36 -0500 |
commit | b9005f35621c564fb70b60223352732eb9cde955 (patch) | |
tree | 0e1dc7cbbefbcf829a0c0cae92095c6255299915 /src/mem/cache/cache_impl.hh | |
parent | ad17b3265178deacb2dce7a98033575c0e98f518 (diff) | |
parent | b5a4d95811db487d946200bf103e2af376db7690 (diff) | |
download | gem5-b9005f35621c564fb70b60223352732eb9cde955.tar.xz |
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
src/cpu/simple/atomic.cc:
merge steve's changes in.
--HG--
extra : convert_revision : a17eda37cd63c9380af6fe68b0aef4b1e1974231
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r-- | src/mem/cache/cache_impl.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index ff35a0749..dac2b93a4 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -206,7 +206,7 @@ Cache<TagStore,Coherence>::handleAccess(PacketPtr &pkt, int & lat, // complete miss (no matching block) if (pkt->req->isLocked() && pkt->isWrite()) { // miss on store conditional... just give up now - pkt->req->setScResult(0); + pkt->req->setExtraData(0); pkt->flags |= SATISFIED; } } @@ -1147,7 +1147,7 @@ Cache<TagStore,Coherence>::CpuSidePort::recvTiming(PacketPtr pkt) } if (pkt->isWrite() && (pkt->req->isLocked())) { - pkt->req->setScResult(1); + pkt->req->setExtraData(1); } myCache()->access(pkt); return true; |