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authorSteve Reinhardt <stever@gmail.com>2008-02-26 20:17:26 -0800
committerSteve Reinhardt <stever@gmail.com>2008-02-26 20:17:26 -0800
commitbdf33239151c7fcc194f6f9b8c62eb313c933755 (patch)
tree813955010ce9920d1f550133c5a19216b066a745 /src/mem/cache/cache_impl.hh
parent8c0baf2ce478b16d351feb1f0ce147049f3a04f6 (diff)
downloadgem5-bdf33239151c7fcc194f6f9b8c62eb313c933755.tar.xz
Cache: better comments particularly regarding writeback situation.
--HG-- extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r--src/mem/cache/cache_impl.hh18
1 files changed, 8 insertions, 10 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d4fbc90a5..15de76532 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -439,12 +439,12 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
}
#if 0
+ /** @todo make the fast write alloc (wh64) work with coherence. */
+
PacketList writebacks;
// If this is a block size write/hint (WH64) allocate the block here
// if the coherence protocol allows it.
- /** @todo make the fast write alloc (wh64) work with coherence. */
- /** @todo Do we want to do fast writes for writebacks as well? */
if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
(pkt->cmd == MemCmd::WriteReq
|| pkt->cmd == MemCmd::WriteInvalidateReq) ) {
@@ -517,6 +517,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
}
+// See comment in cache.hh.
template<class TagStore>
PacketPtr
Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
@@ -529,14 +530,11 @@ Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
return NULL;
}
- if (!blkValid &&
- (cpu_pkt->cmd == MemCmd::Writeback ||
- cpu_pkt->cmd == MemCmd::UpgradeReq)) {
- // For now, writebacks from upper-level caches that
- // completely miss in the cache just go through. If we had
- // "fast write" support (where we could write the whole
- // block w/o fetching new data) we might want to allocate
- // on writeback misses instead.
+ if (!blkValid && (cpu_pkt->cmd == MemCmd::Writeback ||
+ cpu_pkt->cmd == MemCmd::UpgradeReq)) {
+ // Writebacks that weren't allocated in access() and upgrades
+ // from upper-level caches that missed completely just go
+ // through.
return NULL;
}