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authorRon Dreslinski <rdreslin@umich.edu>2006-06-30 17:21:58 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-06-30 17:21:58 -0400
commit7a4929813423c6f72827c58453cb9bd591f1801c (patch)
treebddf49535c38df4e9faf12825861eee80c308229 /src/mem/cache/cache_impl.hh
parent1bdc65b00f40b20dc5c7e97d3c8d8e4b311230a8 (diff)
downloadgem5-7a4929813423c6f72827c58453cb9bd591f1801c.tar.xz
AtomicSimpleCPU with a cache now runs the hello world! test program.
Need to clean up a bunch of flags/hacks in the code. Then onto Timming mode. Functional accesses also work properly, although not exactly how we wanted them. I'll need to clean that up as well. src/cpu/simple/atomic.cc: Atomic CPU needs to set thread context so stats work in cache. Temporarily just use CPU=0 ThreadID=0 src/mem/cache/cache_impl.hh: Need to return success/failure properly still Physical memory object doesn't assert SATISFIED anymore, need to remove that flag src/mem/cache/tags/lru.cc: Doesn't work if the REQ doesn't set it's ASID. Temporary fix use 0 always --HG-- extra : convert_revision : d06a39684af593db699b64df9a29f80c61d8d050
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r--src/mem/cache/cache_impl.hh10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 0cb33461b..aae5cbf01 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -82,6 +82,8 @@ doAtomicAccess(Packet *pkt, bool isCpuSide)
if (isCpuSide)
{
probe(pkt, true);
+ //TEMP ALWAYS SUCCES FOR NOW
+ pkt->result = Packet::Success;
}
else
{
@@ -101,7 +103,11 @@ doFunctionalAccess(Packet *pkt, bool isCpuSide)
{
if (isCpuSide)
{
+ //TEMP USE CPU?THREAD 0 0
+ pkt->req->setThreadContext(0,0);
probe(pkt, true);
+ //TEMP ALWAYS SUCCESFUL FOR NOW
+ pkt->result = Packet::Success;
}
else
{
@@ -594,12 +600,12 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
lat = memSidePort->sendAtomic(busPkt);
- if (!(busPkt->flags & SATISFIED)) {
+/* if (!(busPkt->flags & SATISFIED)) {
// blocked at a higher level, just return
return 0;
}
- misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+*/ misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
CacheBlk::State old_state = (blk) ? blk->status : 0;
tags->handleFill(blk, busPkt,