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authorRon Dreslinski <rdreslin@umich.edu>2006-06-28 14:35:00 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-06-28 14:35:00 -0400
commitfc281d0b64fca8d2809ec462148acb7cf0461ea5 (patch)
treeef772f136f4e1bad0e9de6282201aa6611329fc7 /src/mem/cache/coherence/coherence_protocol.cc
parented8564a6b9f0702a40995d95cc4da54de3d35462 (diff)
downloadgem5-fc281d0b64fca8d2809ec462148acb7cf0461ea5.tar.xz
Backing in more changsets, getting closer to compile
base_cache.cc compiles, continuing on src/SConscript: Add in compilation flags for cache files src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: Back in more fixes, now base_cache compiles src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/miss_queue.hh: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/iic.cc: src/mem/cache/tags/lru.cc: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lru.cc: src/mem/packet.cc: src/mem/packet.hh: src/mem/request.hh: Backing in more changsets, getting closer to compile --HG-- extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
Diffstat (limited to 'src/mem/cache/coherence/coherence_protocol.cc')
-rw-r--r--src/mem/cache/coherence/coherence_protocol.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc
index 107fd2502..9d5b8ef54 100644
--- a/src/mem/cache/coherence/coherence_protocol.cc
+++ b/src/mem/cache/coherence/coherence_protocol.cc
@@ -465,7 +465,7 @@ CacheBlk::State
CoherenceProtocol::getNewState(const Packet * &pkt, CacheBlk::State oldState)
{
CacheBlk::State state = oldState & stateMask;
- int cmd_idx = pkt->cmd.toIndex();
+ int cmd_idx = pkt->cmdToIndex();
assert(0 <= state && state <= stateMax);
assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS);
@@ -498,7 +498,7 @@ CoherenceProtocol::handleBusRequest(BaseCache *cache, Packet * &pkt,
}
CacheBlk::State state = blk->status & stateMask;
- int cmd_idx = pkt->cmd.toIndex();
+ int cmd_idx = pkt->cmdToIndex();
assert(0 <= state && state <= stateMax);
assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS);