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authorRon Dreslinski <rdreslin@umich.edu>2006-06-29 16:07:19 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-06-29 16:07:19 -0400
commiteafb5c4936f7d3233c223d69b435c6be360bbfb2 (patch)
treed331210fbeed1574b64a44275da0c86fd1866fe1 /src/mem/cache/coherence/uni_coherence.cc
parent0d323c753d897bec72884089bc0dc334a64e9eb3 (diff)
downloadgem5-eafb5c4936f7d3233c223d69b435c6be360bbfb2.tar.xz
Still missing prefetch and tags directories as well as cache builder.
Some implementation details were left blank still, need to fill them in. src/SConscript: Reorder build to compile all files first src/mem/cache/cache.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: More changesets pulled, now compiles everything in /miss directory and in the root directory src/mem/packet.hh: Add some more support, need to clean some of it out once everything is working --HG-- extra : convert_revision : ba73676165810edf2c2effaf5fbad8397d6bd800
Diffstat (limited to 'src/mem/cache/coherence/uni_coherence.cc')
-rw-r--r--src/mem/cache/coherence/uni_coherence.cc13
1 files changed, 5 insertions, 8 deletions
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index 68a78e395..5ab706269 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -44,8 +44,8 @@ Packet *
UniCoherence::getPacket()
{
bool unblock = cshrs.isFull();
- Packet * pkt = cshrs.getPkt();
- cshrs.markInService(pkt->senderState);
+ Packet* pkt = cshrs.getReq();
+ cshrs.markInService((MSHR*)pkt->senderState);
if (!cshrs.havePending()) {
cache->clearSlaveRequest(Request_Coherence);
}
@@ -65,15 +65,12 @@ UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
CacheBlk::State &new_state)
{
new_state = 0;
- if (pkt->cmd.isInvalidate()) {
+ if (pkt->isInvalidate()) {
DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n",
- pkt->paddr, blk);
+ pkt->getAddr(), blk);
if (!cache->isTopLevel()) {
// Forward to other caches
- Packet * tmp = new MemPkt();
- tmp->cmd = Invalidate;
- tmp->paddr = pkt->paddr;
- tmp->size = pkt->size;
+ Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
cshrs.allocate(tmp);
cache->setSlaveRequest(Request_Coherence, curTick);
if (cshrs.isFull()) {