Fixes to get single level uni-coherence to work.

Now to try L2 caches in FS.

src/mem/cache/base_cache.hh:
    Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
    Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
    Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Properly forward invalidates in atomic/timing uni-coherence

--HG--
extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7

3 files changed, 32 insertions, 12 deletions

diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh
index a356b3ecc..5a0127c01 100644
--- a/src/mem/cache/coherence/simple_coherence.hh
+++ b/src/mem/cache/coherence/simple_coherence.hh
@@ -160,6 +160,12 @@ class SimpleCoherence
     bool allowFastWrites() { return false; }
 
     bool hasProtocol() { return true; }
+
+    void propogateInvalidate(Packet *pkt, bool isTiming)
+    {
+        //For now we do nothing, asssumes simple coherence is top level of cache
+        return;
+    }
 };
 
 #endif //__SIMPLE_COHERENCE_HH__
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index 464266a29..4ebb2664c 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -76,19 +76,31 @@ UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
 {
     new_state = 0;
     if (pkt->isInvalidate()) {
-        DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n",
-                pkt->getAddr(), blk);
-        // Forward to other caches
-        Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
-        cshrs.allocate(tmp);
-        cache->setSlaveRequest(Request_Coherence, curTick);
-        if (cshrs.isFull()) {
-            cache->setBlockedForSnoop(Blocked_Coherence);
+            DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n",
+                    pkt->getAddr(), blk);
+    }
+    else if (blk) {
+        new_state = blk->status;
+    }
+    return false;
+}
+
+void
+UniCoherence::propogateInvalidate(Packet *pkt, bool isTiming)
+{
+    if (pkt->isInvalidate()) {
+        if (isTiming) {
+            // Forward to other caches
+            Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+            cshrs.allocate(tmp);
+            cache->setSlaveRequest(Request_Coherence, curTick);
+            if (cshrs.isFull())
+                cache->setBlockedForSnoop(Blocked_Coherence);
         }
-    } else {
-        if (blk) {
-            new_state = blk->status;
+        else {
+            Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+            cache->cpuSidePort->sendAtomic(tmp);
+            delete tmp;
         }
     }
-    return false;
 }
diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh
index 60da7a36e..4f69d52e2 100644
--- a/src/mem/cache/coherence/uni_coherence.hh
+++ b/src/mem/cache/coherence/uni_coherence.hh
@@ -139,6 +139,8 @@ class UniCoherence
     bool allowFastWrites() { return true; }
 
     bool hasProtocol() { return false; }
+
+    void propogateInvalidate(Packet *pkt, bool isTiming);
 };
 
 #endif //__UNI_COHERENCE_HH__