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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-28 14:35:00 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-28 14:35:00 -0400 |
commit | fc281d0b64fca8d2809ec462148acb7cf0461ea5 (patch) | |
tree | ef772f136f4e1bad0e9de6282201aa6611329fc7 /src/mem/cache/miss/blocking_buffer.cc | |
parent | ed8564a6b9f0702a40995d95cc4da54de3d35462 (diff) | |
download | gem5-fc281d0b64fca8d2809ec462148acb7cf0461ea5.tar.xz |
Backing in more changsets, getting closer to compile
base_cache.cc compiles, continuing on
src/SConscript:
Add in compilation flags for cache files
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Back in more fixes, now base_cache compiles
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lru.cc:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/request.hh:
Backing in more changsets, getting closer to compile
--HG--
extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
Diffstat (limited to 'src/mem/cache/miss/blocking_buffer.cc')
-rw-r--r-- | src/mem/cache/miss/blocking_buffer.cc | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc index 621855c3d..912a0f5bd 100644 --- a/src/mem/cache/miss/blocking_buffer.cc +++ b/src/mem/cache/miss/blocking_buffer.cc @@ -73,7 +73,7 @@ void BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time) { Addr blk_addr = pkt->paddr & ~(Addr)(blk_size - 1); - if (pkt->cmd.isWrite() && (pkt->isUncacheable() || !writeAllocate || + if (pkt->cmd.isWrite() && (pkt->req->isUncacheable() || !writeAllocate || pkt->cmd.isNoResponse())) { if (pkt->cmd.isNoResponse()) { wb.allocateAsBuffer(pkt); @@ -93,7 +93,7 @@ BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time) } else { miss.allocate(pkt->cmd, blk_addr, pkt->req->asid, blk_size, pkt); } - if (!pkt->isUncacheable()) { + if (!pkt->req->isUncacheable()) { miss.pkt->flags |= CACHE_LINE_FILL; } cache->setBlocked(Blocked_NoMSHRs); @@ -186,12 +186,12 @@ BlockingBuffer::handleResponse(Packet * &pkt, Tick time) } void -BlockingBuffer::squash(int thread_number) +BlockingBuffer::squash(int req->getThreadNum()ber) { - if (miss.threadNum == thread_number) { + if (miss.setThreadNum() == req->getThreadNum()ber) { Packet * target = miss.getTarget(); miss.popTarget(); - assert(target->thread_num == thread_number); + assert(target->req->setThreadNum() == req->getThreadNum()ber); if (target->completionEvent != NULL) { delete target->completionEvent; } @@ -207,7 +207,7 @@ BlockingBuffer::squash(int thread_number) } void -BlockingBuffer::doWriteback(Addr addr, int asid, ExecContext *xc, +BlockingBuffer::doWriteback(Addr addr, int asid, int size, uint8_t *data, bool compressed) { @@ -224,18 +224,14 @@ BlockingBuffer::doWriteback(Addr addr, int asid, ExecContext *xc, * @todo Need to find a way to charge the writeback to the "correct" * thread. */ - pkt->xc = xc; - if (xc) - pkt->thread_num = xc->getThreadNum(); - else - pkt->thread_num = 0; + pkt->req->setThreadNum() = 0; pkt->cmd = Writeback; if (compressed) { pkt->flags |= COMPRESSED; } - writebacks[pkt->thread_num]++; + writebacks[pkt->req->getThreadNum()]++; wb.allocateAsBuffer(pkt); cache->setMasterRequest(Request_WB, curTick); @@ -247,7 +243,7 @@ BlockingBuffer::doWriteback(Addr addr, int asid, ExecContext *xc, void BlockingBuffer::doWriteback(Packet * &pkt) { - writebacks[pkt->thread_num]++; + writebacks[pkt->req->getThreadNum()]++; wb.allocateAsBuffer(pkt); |