diff options
author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
commit | 5fbf3aa47112b3d28971c0bab604ce9cc3f67b16 (patch) | |
tree | f38e2827f802c205d8373d68d125a8d17aa5e4ee /src/mem/cache/miss/blocking_buffer.hh | |
parent | 51e3688701fe66987f96c5ddc5b8f111f4ad94d6 (diff) | |
download | gem5-5fbf3aa47112b3d28971c0bab604ce9cc3f67b16.tar.xz |
Turn cache MissQueue/BlockingBuffer into virtual object
instead of template parameter.
--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
Diffstat (limited to 'src/mem/cache/miss/blocking_buffer.hh')
-rw-r--r-- | src/mem/cache/miss/blocking_buffer.hh | 60 |
1 files changed, 5 insertions, 55 deletions
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh index a952c688c..205068a8c 100644 --- a/src/mem/cache/miss/blocking_buffer.hh +++ b/src/mem/cache/miss/blocking_buffer.hh @@ -39,16 +39,13 @@ #include <vector> #include "base/misc.hh" // for fatal() +#include "mem/cache/miss/miss_buffer.hh" #include "mem/cache/miss/mshr.hh" -#include "base/statistics.hh" - -class BaseCache; -class BasePrefetcher; /** * Miss and writeback storage for a blocking cache. */ -class BlockingBuffer +class BlockingBuffer : public MissBuffer { protected: /** Miss storage. */ @@ -56,38 +53,13 @@ protected: /** WB storage. */ MSHR wb; - //Params - - /** Allocate on write misses. */ - const bool writeAllocate; - - /** Pointer to the parent cache. */ - BaseCache* cache; - - BasePrefetcher* prefetcher; - - /** Block size of the parent cache. */ - int blkSize; - - // Statistics - /** - * @addtogroup CacheStatistics - * @{ - */ - /** Number of blocks written back per thread. */ - Stats::Vector<> writebacks; - - /** - * @} - */ - public: /** * Builds and initializes this buffer. * @param write_allocate If true, treat write misses the same as reads. */ BlockingBuffer(bool write_allocate) - : writeAllocate(write_allocate) + : MissBuffer(write_allocate) { } @@ -98,14 +70,6 @@ public: void regStats(const std::string &name); /** - * Called by the parent cache to set the back pointer. - * @param _cache A pointer to the parent cache. - */ - void setCache(BaseCache *_cache); - - void setPrefetcher(BasePrefetcher *_prefetcher); - - /** * Handle a cache miss properly. Requests the bus and marks the cache as * blocked. * @param pkt The request that missed in the cache. @@ -184,12 +148,7 @@ public: * @param asid The address space id. * @return A pointer to miss if it matches. */ - MSHR* findMSHR(Addr addr) - { - if (miss.addr == addr && miss.pkt) - return &miss; - return NULL; - } + MSHR* findMSHR(Addr addr); /** * Searches for the supplied address in the write buffer. @@ -198,16 +157,7 @@ public: * @param writes List of pointers to the matching writes. * @return True if there is a matching write. */ - bool findWrites(Addr addr, std::vector<MSHR*>& writes) - { - if (wb.addr == addr && wb.pkt) { - writes.push_back(&wb); - return true; - } - return false; - } - - + bool findWrites(Addr addr, std::vector<MSHR*>& writes); /** * Perform a writeback of dirty data to the given address. |