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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
commit | 5fbf3aa47112b3d28971c0bab604ce9cc3f67b16 (patch) | |
tree | f38e2827f802c205d8373d68d125a8d17aa5e4ee /src/mem/cache/miss/miss_buffer.cc | |
parent | 51e3688701fe66987f96c5ddc5b8f111f4ad94d6 (diff) | |
download | gem5-5fbf3aa47112b3d28971c0bab604ce9cc3f67b16.tar.xz |
Turn cache MissQueue/BlockingBuffer into virtual object
instead of template parameter.
--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
Diffstat (limited to 'src/mem/cache/miss/miss_buffer.cc')
-rw-r--r-- | src/mem/cache/miss/miss_buffer.cc | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/src/mem/cache/miss/miss_buffer.cc b/src/mem/cache/miss/miss_buffer.cc new file mode 100644 index 000000000..4d9cd0958 --- /dev/null +++ b/src/mem/cache/miss/miss_buffer.cc @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2003-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Erik Hallnor + */ + +#include "cpu/smt.hh" //for maxThreadsPerCPU +#include "mem/cache/base_cache.hh" +#include "mem/cache/miss/miss_buffer.hh" +#include "mem/cache/prefetch/base_prefetcher.hh" + +/** + * @todo Move writebacks into shared BaseBuffer class. + */ +void +MissBuffer::regStats(const std::string &name) +{ + using namespace Stats; + writebacks + .init(maxThreadsPerCPU) + .name(name + ".writebacks") + .desc("number of writebacks") + .flags(total) + ; +} + +void +MissBuffer::setCache(BaseCache *_cache) +{ + cache = _cache; + blkSize = cache->getBlockSize(); +} + +void +MissBuffer::setPrefetcher(BasePrefetcher *_prefetcher) +{ + prefetcher = _prefetcher; +} |