First pass, now compiles with current head of tree.

Compile and initialization work, still working on functionality.

src/mem/cache/base_cache.cc:
    Temp fix for cpu's use of getPort functionality.  CPU's will need to be ported to the new connector objects.
    Also, all packets have to have data or the delete fails.
src/mem/cache/cache.hh:
    Fix function prototypes so overloading works
src/mem/cache/cache_impl.hh:
    fix functions to match virtual base class
src/mem/cache/miss/miss_queue.cc:
    Packets havve to have data, or delete fails
src/python/m5/objects/BaseCache.py:
    Update for newmem

--HG--
extra : convert_revision : 2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb

1 files changed, 2 insertions, 1 deletions

diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 99ebab017..da0448ad3 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -58,9 +58,10 @@ MissQueue::MissQueue(int numMSHRs, int numTargets, int write_buffers,
 void
 MissQueue::regStats(const string &name)
 {
-    Request temp_req;
+    Request temp_req((Addr) NULL, 4, 0);
     Packet::Command temp_cmd = Packet::ReadReq;
     Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
+    temp_pkt.allocate();
 
     using namespace Stats;