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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-15 16:21:46 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-15 16:21:46 -0400 |
commit | d5ac1cb51f2e08531794e1dcbb17e47f51041c4f (patch) | |
tree | 79d49fad55c832837f4cf2a8453df72ba83d1bee /src/mem/cache/miss/miss_queue.cc | |
parent | d0d0d7b636c20ad0fafec885c246711ec4218fff (diff) | |
download | gem5-d5ac1cb51f2e08531794e1dcbb17e47f51041c4f.tar.xz |
Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.
-Basically removed the ASID from places it is no longer needed due to PageTable
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
Remove asid where it wasn't neccesary anymore due to Page Table
--HG--
extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28
Diffstat (limited to 'src/mem/cache/miss/miss_queue.cc')
-rw-r--r-- | src/mem/cache/miss/miss_queue.cc | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc index 4a3dc1062..76fb25716 100644 --- a/src/mem/cache/miss/miss_queue.cc +++ b/src/mem/cache/miss/miss_queue.cc @@ -410,7 +410,7 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1); MSHR* mshr = NULL; if (!pkt->req->isUncacheable()) { - mshr = mq.findMatch(blkAddr, pkt->req->getAsid()); + mshr = mq.findMatch(blkAddr); if (mshr) { //@todo remove hw_pf here mshr_hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; @@ -454,12 +454,12 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) } MSHR* -MissQueue::fetchBlock(Addr addr, int asid, int blk_size, Tick time, +MissQueue::fetchBlock(Addr addr, int blk_size, Tick time, Packet * &target) { Addr blkAddr = addr & ~(Addr)(blk_size - 1); - assert(mq.findMatch(addr, asid) == NULL); - MSHR *mshr = mq.allocateFetch(blkAddr, asid, blk_size, target); + assert(mq.findMatch(addr) == NULL); + MSHR *mshr = mq.allocateFetch(blkAddr, blk_size, target); mshr->order = order++; mshr->pkt->flags |= CACHE_LINE_FILL; if (mq.isFull()) { @@ -697,19 +697,19 @@ MissQueue::squash(int threadNum) } MSHR* -MissQueue::findMSHR(Addr addr, int asid) const +MissQueue::findMSHR(Addr addr) const { - return mq.findMatch(addr,asid); + return mq.findMatch(addr); } bool -MissQueue::findWrites(Addr addr, int asid, vector<MSHR*> &writes) const +MissQueue::findWrites(Addr addr, vector<MSHR*> &writes) const { - return wb.findMatches(addr,asid,writes); + return wb.findMatches(addr,writes); } void -MissQueue::doWriteback(Addr addr, int asid, +MissQueue::doWriteback(Addr addr, int size, uint8_t *data, bool compressed) { // Generate request @@ -740,9 +740,9 @@ MissQueue::doWriteback(Packet * &pkt) MSHR* -MissQueue::allocateTargetList(Addr addr, int asid) +MissQueue::allocateTargetList(Addr addr) { - MSHR* mshr = mq.allocateTargetList(addr, asid, blkSize); + MSHR* mshr = mq.allocateTargetList(addr, blkSize); mshr->pkt->flags |= CACHE_LINE_FILL; if (mq.isFull()) { cache->setBlocked(Blocked_NoMSHRs); |