Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.

-Basically removed the ASID from places it is no longer needed due to PageTable

src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
    Remove asid where it wasn't neccesary anymore due to Page Table

--HG--
extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28

1 files changed, 5 insertions, 5 deletions

diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index c558df956..505d1f90c 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -228,7 +228,7 @@ class MissQueue
      * @param time The time the miss is detected.
      * @param target The target for the fetch.
      */
-    MSHR* fetchBlock(Addr addr, int asid, int blk_size, Tick time,
+    MSHR* fetchBlock(Addr addr, int blk_size, Tick time,
                      Packet * &target);
 
     /**
@@ -289,7 +289,7 @@ class MissQueue
      * @warning Currently only searches the miss queue. If non write allocate
      * might need to search the write buffer for coherence.
      */
-    MSHR* findMSHR(Addr addr, int asid) const;
+    MSHR* findMSHR(Addr addr) const;
 
     /**
      * Searches for the supplied address in the write buffer.
@@ -298,7 +298,7 @@ class MissQueue
      * @param writes The list of writes that match the address.
      * @return True if any writes are found
      */
-    bool findWrites(Addr addr, int asid, std::vector<MSHR*>& writes) const;
+    bool findWrites(Addr addr, std::vector<MSHR*>& writes) const;
 
     /**
      * Perform a writeback of dirty data to the given address.
@@ -309,7 +309,7 @@ class MissQueue
      * @param data The data to write, can be NULL.
      * @param compressed True if the data is compressed.
      */
-    void doWriteback(Addr addr, int asid,
+    void doWriteback(Addr addr,
                      int size, uint8_t *data, bool compressed);
 
     /**
@@ -342,7 +342,7 @@ class MissQueue
      * @param asid The address space ID.
      * @return A pointer to the allocated MSHR.
      */
-    MSHR* allocateTargetList(Addr addr, int asid);
+    MSHR* allocateTargetList(Addr addr);
 
 };