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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
commit | 5fbf3aa47112b3d28971c0bab604ce9cc3f67b16 (patch) | |
tree | f38e2827f802c205d8373d68d125a8d17aa5e4ee /src/mem/cache/miss/miss_queue.hh | |
parent | 51e3688701fe66987f96c5ddc5b8f111f4ad94d6 (diff) | |
download | gem5-5fbf3aa47112b3d28971c0bab604ce9cc3f67b16.tar.xz |
Turn cache MissQueue/BlockingBuffer into virtual object
instead of template parameter.
--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
Diffstat (limited to 'src/mem/cache/miss/miss_queue.hh')
-rw-r--r-- | src/mem/cache/miss/miss_queue.hh | 30 |
1 files changed, 4 insertions, 26 deletions
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh index b67a896f4..1f9bb1e0c 100644 --- a/src/mem/cache/miss/miss_queue.hh +++ b/src/mem/cache/miss/miss_queue.hh @@ -38,19 +38,18 @@ #include <vector> +#include "mem/cache/miss/miss_buffer.hh" #include "mem/cache/miss/mshr.hh" #include "mem/cache/miss/mshr_queue.hh" #include "base/statistics.hh" -class BaseCache; -class BasePrefetcher; /** * Manages cache misses and writebacks. Contains MSHRs to store miss data * and the writebuffer for writes/writebacks. * @todo need to handle data on writes better (encapsulate). * @todo need to make replacements/writebacks happen in Cache::access */ -class MissQueue +class MissQueue : public MissBuffer { protected: /** The MSHRs. */ @@ -66,16 +65,6 @@ class MissQueue const int numTarget; /** The number of write buffers. */ const int writeBuffers; - /** True if the cache should allocate on a write miss. */ - const bool writeAllocate; - /** Pointer to the parent cache. */ - BaseCache* cache; - - /** The Prefetcher */ - BasePrefetcher *prefetcher; - - /** The block size of the parent cache. */ - int blkSize; /** Increasing order number assigned to each incoming request. */ uint64_t order; @@ -87,9 +76,6 @@ class MissQueue * @addtogroup CacheStatistics * @{ */ - /** Number of blocks written back per thread. */ - Stats::Vector<> writebacks; - /** Number of misses that hit in the MSHRs per command and thread. */ Stats::Vector<> mshr_hits[NUM_MEM_CMDS]; /** Demand misses that hit in the MSHRs. */ @@ -204,14 +190,6 @@ class MissQueue void regStats(const std::string &name); /** - * Called by the parent cache to set the back pointer. - * @param _cache A pointer to the parent cache. - */ - void setCache(BaseCache *_cache); - - void setPrefetcher(BasePrefetcher *_prefetcher); - - /** * Handle a cache miss properly. Either allocate an MSHR for the request, * or forward it through the write buffer. * @param pkt The request that missed in the cache. @@ -289,7 +267,7 @@ class MissQueue * @warning Currently only searches the miss queue. If non write allocate * might need to search the write buffer for coherence. */ - MSHR* findMSHR(Addr addr) const; + MSHR* findMSHR(Addr addr); /** * Searches for the supplied address in the write buffer. @@ -298,7 +276,7 @@ class MissQueue * @param writes The list of writes that match the address. * @return True if any writes are found */ - bool findWrites(Addr addr, std::vector<MSHR*>& writes) const; + bool findWrites(Addr addr, std::vector<MSHR*>& writes); /** * Perform a writeback of dirty data to the given address. |