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authorRon Dreslinski <rdreslin@umich.edu>2006-06-29 16:07:19 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-06-29 16:07:19 -0400
commiteafb5c4936f7d3233c223d69b435c6be360bbfb2 (patch)
treed331210fbeed1574b64a44275da0c86fd1866fe1 /src/mem/cache/miss/mshr.cc
parent0d323c753d897bec72884089bc0dc334a64e9eb3 (diff)
downloadgem5-eafb5c4936f7d3233c223d69b435c6be360bbfb2.tar.xz
Still missing prefetch and tags directories as well as cache builder.
Some implementation details were left blank still, need to fill them in. src/SConscript: Reorder build to compile all files first src/mem/cache/cache.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: More changesets pulled, now compiles everything in /miss directory and in the root directory src/mem/packet.hh: Add some more support, need to clean some of it out once everything is working --HG-- extra : convert_revision : ba73676165810edf2c2effaf5fbad8397d6bd800
Diffstat (limited to 'src/mem/cache/miss/mshr.cc')
-rw-r--r--src/mem/cache/miss/mshr.cc35
1 files changed, 17 insertions, 18 deletions
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 5c3c9fd1d..fe8cbeea4 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -50,13 +50,15 @@ MSHR::MSHR()
{
inService = false;
ntargets = 0;
- setThreadNum() = -1;
+ threadNum = -1;
}
void
MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
Packet * &target)
{
+ assert("NEED TO FIX YET\n" && 0);
+#if 0
assert(targets.empty());
addr = _addr;
asid = _asid;
@@ -74,6 +76,7 @@ MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
pkt->req = target->req;
allocateTarget(target);
}
+#endif
}
// Since we aren't sure if data is being used, don't copy here.
@@ -83,17 +86,13 @@ MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
void
MSHR::allocateAsBuffer(Packet * &target)
{
- addr = target->paddr;
- asid = target->req->asid;
- setThreadNum() = target->req->getThreadNum();
- pkt = new Packet();
- pkt->addr = target->addr;
- pkt->dest = target->dest;
- pkt->cmd = target->cmd;
- pkt->size = target->size;
- pkt->req = target->req;
- pkt->data = new uint8_t[target->size];
- pkt->senderState = this;
+ addr = target->getAddr();
+ asid = target->req->getAsid();
+ threadNum = target->req->getThreadNum();
+ pkt = new Packet(target->req, target->cmd, -1);
+ uint8_t *new_data = new uint8_t[target->getSize()];
+ pkt->dataDynamicArray<uint8_t>(new_data);
+ pkt->senderState = (Packet::SenderState*)this;
pkt->time = curTick;
}
@@ -117,11 +116,11 @@ MSHR::allocateTarget(Packet * &target)
//If we append an invalidate and we issued a read to the bus,
//but now have some pending writes, we need to move
//the invalidate to before the first non-read
- if (inService && pkt->cmd.isRead() && target->cmd.isInvalidate()) {
+ if (inService && pkt->isRead() && target->isInvalidate()) {
std::list<Packet *> temp;
while (!targets.empty()) {
- if (!targets.front()->cmd.isRead()) break;
+ if (!targets.front()->isRead()) break;
//Place on top of temp stack
temp.push_front(targets.front());
//Remove from targets
@@ -148,8 +147,8 @@ MSHR::allocateTarget(Packet * &target)
* @todo really prioritize the target commands.
*/
- if (!inService && target->cmd.isWrite()) {
- pkt->cmd = WriteReq;
+ if (!inService && target->isWrite()) {
+ pkt->cmd = Packet::WriteReq;
}
}
@@ -162,14 +161,14 @@ MSHR::dump()
"inService: %d thread: %d\n"
"Addr: %x asid: %d ntargets %d\n"
"Targets:\n",
- inService, getThreadNum(), addr, asid, ntargets);
+ inService, threadNum, addr, asid, ntargets);
TargetListIterator tar_it = targets.begin();
for (int i = 0; i < ntargets; i++) {
assert(tar_it != targets.end());
ccprintf(cerr, "\t%d: Addr: %x cmd: %d\n",
- i, (*tar_it)->paddr, (*tar_it)->cmdToIndex());
+ i, (*tar_it)->getAddr(), (*tar_it)->cmdToIndex());
tar_it++;
}