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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-10 17:16:15 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-10 17:16:15 -0400 |
| commit | 6592045cbc138306474d24d60daa222a07673fe2 (patch) | |
| tree | 5fb86438978286223db6f4a9faf47a516d9d3d6b /src/mem/cache/miss/mshr.cc | |
| parent | 5584e2b26eccb5d2bf445b8b0b2040449d0b0a77 (diff) | |
| download | gem5-6592045cbc138306474d24d60daa222a07673fe2.tar.xz | |
Some fixes so that MSHR's are matched and we don't issue overlapping requests with detailed cpu
src/mem/cache/base_cache.cc:
If we still have outstanding requests, need to schedule event again
src/mem/cache/miss/miss_queue.cc:
Need to use block size so overlapping requests match in the MSHR's
src/mem/cache/miss/mshr.cc:
Actually save the address, otherwise we can't match MSHR's
--HG--
extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
Diffstat (limited to 'src/mem/cache/miss/mshr.cc')
| -rw-r--r-- | src/mem/cache/miss/mshr.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc index 1a85d3018..db2f40c56 100644 --- a/src/mem/cache/miss/mshr.cc +++ b/src/mem/cache/miss/mshr.cc @@ -57,6 +57,7 @@ void MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size, Packet * &target) { + addr = _addr; if (target) { //Have a request, just use it |