Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.

-Basically removed the ASID from places it is no longer needed due to PageTable

src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
    Remove asid where it wasn't neccesary anymore due to Page Table

--HG--
extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28

1 files changed, 7 insertions, 7 deletions

diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index 6516a99f8..f13f48dec 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -55,7 +55,7 @@ MSHRQueue::~MSHRQueue()
 }
 
 MSHR*
-MSHRQueue::findMatch(Addr addr, int asid) const
+MSHRQueue::findMatch(Addr addr) const
 {
     MSHR::ConstIterator i = allocatedList.begin();
     MSHR::ConstIterator end = allocatedList.end();
@@ -69,7 +69,7 @@ MSHRQueue::findMatch(Addr addr, int asid) const
 }
 
 bool
-MSHRQueue::findMatches(Addr addr, int asid, vector<MSHR*>& matches) const
+MSHRQueue::findMatches(Addr addr, vector<MSHR*>& matches) const
 {
     // Need an empty vector
     assert(matches.empty());
@@ -136,7 +136,7 @@ MSHRQueue::allocate(Packet * &pkt, int size)
         mshr->allocateAsBuffer(pkt);
     } else {
         assert(size !=0);
-        mshr->allocate(pkt->cmd, aligned_addr, pkt->req->getAsid(), size, pkt);
+        mshr->allocate(pkt->cmd, aligned_addr, size, pkt);
         allocatedTargets += 1;
     }
     mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
@@ -147,12 +147,12 @@ MSHRQueue::allocate(Packet * &pkt, int size)
 }
 
 MSHR*
-MSHRQueue::allocateFetch(Addr addr, int asid, int size, Packet * &target)
+MSHRQueue::allocateFetch(Addr addr, int size, Packet * &target)
 {
     MSHR *mshr = freeList.front();
     assert(mshr->getNumTargets() == 0);
     freeList.pop_front();
-    mshr->allocate(Packet::ReadReq, addr, asid, size, target);
+    mshr->allocate(Packet::ReadReq, addr, size, target);
     mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
     mshr->readyIter = pendingList.insert(pendingList.end(), mshr);
 
@@ -161,13 +161,13 @@ MSHRQueue::allocateFetch(Addr addr, int asid, int size, Packet * &target)
 }
 
 MSHR*
-MSHRQueue::allocateTargetList(Addr addr, int asid, int size)
+MSHRQueue::allocateTargetList(Addr addr, int size)
 {
     MSHR *mshr = freeList.front();
     assert(mshr->getNumTargets() == 0);
     freeList.pop_front();
     Packet * dummy;
-    mshr->allocate(Packet::ReadReq, addr, asid, size, dummy);
+    mshr->allocate(Packet::ReadReq, addr, size, dummy);
     mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
     mshr->inService = true;
     ++inServiceMSHRs;