Make memory commands dense again to avoid cache stat table explosion.

Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.

--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b

9 files changed, 76 insertions, 81 deletions

diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index a1af88341..e8ff26880 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -90,7 +90,7 @@ BlockingBuffer::getPacket()
 }
 
 void
-BlockingBuffer::setBusCmd(PacketPtr &pkt, Packet::Command cmd)
+BlockingBuffer::setBusCmd(PacketPtr &pkt, MemCmd cmd)
 {
     MSHR *mshr = (MSHR*) pkt->senderState;
     mshr->originalCmd = pkt->cmd;
@@ -189,7 +189,7 @@ BlockingBuffer::doWriteback(Addr addr,
 {
     // Generate request
     Request * req = new Request(addr, size, 0);
-    PacketPtr pkt = new Packet(req, Packet::Writeback, -1);
+    PacketPtr pkt = new Packet(req, MemCmd::Writeback, -1);
     pkt->allocate();
     if (data) {
         std::memcpy(pkt->getPtr<uint8_t>(), data, size);
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index 24386a249..86b24d539 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -104,7 +104,7 @@ public:
      * @param pkt The request to update.
      * @param cmd The bus command to use.
      */
-    void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
+    void setBusCmd(PacketPtr &pkt, MemCmd cmd);
 
     /**
      * Restore the original command in case of a bus transmission error.
diff --git a/src/mem/cache/miss/miss_buffer.hh b/src/mem/cache/miss/miss_buffer.hh
index 3e3080578..9a86db304 100644
--- a/src/mem/cache/miss/miss_buffer.hh
+++ b/src/mem/cache/miss/miss_buffer.hh
@@ -123,7 +123,7 @@ class MissBuffer
      * @param pkt The request to update.
      * @param cmd The bus command to use.
      */
-    virtual void setBusCmd(PacketPtr &pkt, Packet::Command cmd) = 0;
+    virtual void setBusCmd(PacketPtr &pkt, MemCmd cmd) = 0;
 
     /**
      * Restore the original command in case of a bus transmission error.
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 1d3e22326..25b8fcbeb 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -67,17 +67,12 @@ MissQueue::regStats(const string &name)
 {
     MissBuffer::regStats(name);
 
-    Request temp_req((Addr) NULL, 4, 0);
-    Packet::Command temp_cmd = Packet::ReadReq;
-    Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
-    temp_pkt.allocate();
-
     using namespace Stats;
 
     // MSHR hit statistics
-    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = temp_pkt.cmdIdxToString(cmd);
+    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+        MemCmd cmd(access_idx);
+        const string &cstr = cmd.toString();
 
         mshr_hits[access_idx]
             .init(maxThreadsPerCPU)
@@ -92,20 +87,20 @@ MissQueue::regStats(const string &name)
         .desc("number of demand (read+write) MSHR hits")
         .flags(total)
         ;
-    demandMshrHits = mshr_hits[Packet::ReadReq] + mshr_hits[Packet::WriteReq];
+    demandMshrHits = mshr_hits[MemCmd::ReadReq] + mshr_hits[MemCmd::WriteReq];
 
     overallMshrHits
         .name(name + ".overall_mshr_hits")
         .desc("number of overall MSHR hits")
         .flags(total)
         ;
-    overallMshrHits = demandMshrHits + mshr_hits[Packet::SoftPFReq] +
-        mshr_hits[Packet::HardPFReq];
+    overallMshrHits = demandMshrHits + mshr_hits[MemCmd::SoftPFReq] +
+        mshr_hits[MemCmd::HardPFReq];
 
     // MSHR miss statistics
-    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = temp_pkt.cmdIdxToString(cmd);
+    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+        MemCmd cmd(access_idx);
+        const string &cstr = cmd.toString();
 
         mshr_misses[access_idx]
             .init(maxThreadsPerCPU)
@@ -120,20 +115,20 @@ MissQueue::regStats(const string &name)
         .desc("number of demand (read+write) MSHR misses")
         .flags(total)
         ;
-    demandMshrMisses = mshr_misses[Packet::ReadReq] + mshr_misses[Packet::WriteReq];
+    demandMshrMisses = mshr_misses[MemCmd::ReadReq] + mshr_misses[MemCmd::WriteReq];
 
     overallMshrMisses
         .name(name + ".overall_mshr_misses")
         .desc("number of overall MSHR misses")
         .flags(total)
         ;
-    overallMshrMisses = demandMshrMisses + mshr_misses[Packet::SoftPFReq] +
-        mshr_misses[Packet::HardPFReq];
+    overallMshrMisses = demandMshrMisses + mshr_misses[MemCmd::SoftPFReq] +
+        mshr_misses[MemCmd::HardPFReq];
 
     // MSHR miss latency statistics
-    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = temp_pkt.cmdIdxToString(cmd);
+    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+        MemCmd cmd(access_idx);
+        const string &cstr = cmd.toString();
 
         mshr_miss_latency[access_idx]
             .init(maxThreadsPerCPU)
@@ -148,8 +143,8 @@ MissQueue::regStats(const string &name)
         .desc("number of demand (read+write) MSHR miss cycles")
         .flags(total)
         ;
-    demandMshrMissLatency = mshr_miss_latency[Packet::ReadReq]
-        + mshr_miss_latency[Packet::WriteReq];
+    demandMshrMissLatency = mshr_miss_latency[MemCmd::ReadReq]
+        + mshr_miss_latency[MemCmd::WriteReq];
 
     overallMshrMissLatency
         .name(name + ".overall_mshr_miss_latency")
@@ -157,12 +152,12 @@ MissQueue::regStats(const string &name)
         .flags(total)
         ;
     overallMshrMissLatency = demandMshrMissLatency +
-        mshr_miss_latency[Packet::SoftPFReq] + mshr_miss_latency[Packet::HardPFReq];
+        mshr_miss_latency[MemCmd::SoftPFReq] + mshr_miss_latency[MemCmd::HardPFReq];
 
     // MSHR uncacheable statistics
-    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = temp_pkt.cmdIdxToString(cmd);
+    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+        MemCmd cmd(access_idx);
+        const string &cstr = cmd.toString();
 
         mshr_uncacheable[access_idx]
             .init(maxThreadsPerCPU)
@@ -177,14 +172,14 @@ MissQueue::regStats(const string &name)
         .desc("number of overall MSHR uncacheable misses")
         .flags(total)
         ;
-    overallMshrUncacheable = mshr_uncacheable[Packet::ReadReq]
-        + mshr_uncacheable[Packet::WriteReq] + mshr_uncacheable[Packet::SoftPFReq]
-        + mshr_uncacheable[Packet::HardPFReq];
+    overallMshrUncacheable = mshr_uncacheable[MemCmd::ReadReq]
+        + mshr_uncacheable[MemCmd::WriteReq] + mshr_uncacheable[MemCmd::SoftPFReq]
+        + mshr_uncacheable[MemCmd::HardPFReq];
 
     // MSHR miss latency statistics
-    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = temp_pkt.cmdIdxToString(cmd);
+    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+        MemCmd cmd(access_idx);
+        const string &cstr = cmd.toString();
 
         mshr_uncacheable_lat[access_idx]
             .init(maxThreadsPerCPU)
@@ -199,16 +194,16 @@ MissQueue::regStats(const string &name)
         .desc("number of overall MSHR uncacheable cycles")
         .flags(total)
         ;
-    overallMshrUncacheableLatency = mshr_uncacheable_lat[Packet::ReadReq]
-        + mshr_uncacheable_lat[Packet::WriteReq]
-        + mshr_uncacheable_lat[Packet::SoftPFReq]
-        + mshr_uncacheable_lat[Packet::HardPFReq];
+    overallMshrUncacheableLatency = mshr_uncacheable_lat[MemCmd::ReadReq]
+        + mshr_uncacheable_lat[MemCmd::WriteReq]
+        + mshr_uncacheable_lat[MemCmd::SoftPFReq]
+        + mshr_uncacheable_lat[MemCmd::HardPFReq];
 
 #if 0
     // MSHR access formulas
-    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = temp_pkt.cmdIdxToString(cmd);
+    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+        MemCmd cmd(access_idx);
+        const string &cstr = cmd.toString();
 
         mshrAccesses[access_idx]
             .name(name + "." + cstr + "_mshr_accesses")
@@ -237,9 +232,9 @@ MissQueue::regStats(const string &name)
 #endif
 
     // MSHR miss rate formulas
-    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = temp_pkt.cmdIdxToString(cmd);
+    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+        MemCmd cmd(access_idx);
+        const string &cstr = cmd.toString();
 
         mshrMissRate[access_idx]
             .name(name + "." + cstr + "_mshr_miss_rate")
@@ -266,9 +261,9 @@ MissQueue::regStats(const string &name)
     overallMshrMissRate = overallMshrMisses / cache->overallAccesses;
 
     // mshrMiss latency formulas
-    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = temp_pkt.cmdIdxToString(cmd);
+    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+        MemCmd cmd(access_idx);
+        const string &cstr = cmd.toString();
 
         avgMshrMissLatency[access_idx]
             .name(name + "." + cstr + "_avg_mshr_miss_latency")
@@ -295,9 +290,9 @@ MissQueue::regStats(const string &name)
     overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
 
     // mshrUncacheable latency formulas
-    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = temp_pkt.cmdIdxToString(cmd);
+    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+        MemCmd cmd(access_idx);
+        const string &cstr = cmd.toString();
 
         avgMshrUncacheableLatency[access_idx]
             .name(name + "." + cstr + "_avg_mshr_uncacheable_latency")
@@ -351,7 +346,7 @@ MissQueue::allocateMiss(PacketPtr &pkt, int size, Tick time)
     if (mq.isFull()) {
         cache->setBlocked(Blocked_NoMSHRs);
     }
-    if (pkt->cmd != Packet::HardPFReq) {
+    if (pkt->cmd != MemCmd::HardPFReq) {
         //If we need to request the bus (not on HW prefetch), do so
         cache->setMasterRequest(Request_MSHR, time);
     }
@@ -500,17 +495,17 @@ MissQueue::getPacket()
 }
 
 void
-MissQueue::setBusCmd(PacketPtr &pkt, Packet::Command cmd)
+MissQueue::setBusCmd(PacketPtr &pkt, MemCmd cmd)
 {
     assert(pkt->senderState != 0);
     MSHR * mshr = (MSHR*)pkt->senderState;
     mshr->originalCmd = pkt->cmd;
-    if (cmd == Packet::UpgradeReq || cmd == Packet::InvalidateReq) {
+    if (cmd == MemCmd::UpgradeReq || cmd == MemCmd::InvalidateReq) {
         pkt->flags |= NO_ALLOCATE;
         pkt->flags &= ~CACHE_LINE_FILL;
     }
     else if (!pkt->req->isUncacheable() && !pkt->isNoAllocate() &&
-             (cmd & (1 << 6)/*NeedsResponse*/)) {
+             cmd.needsResponse()) {
         pkt->flags |= CACHE_LINE_FILL;
     }
     if (pkt->isCacheFill() || pkt->isNoAllocate())
@@ -552,7 +547,7 @@ MissQueue::markInService(PacketPtr &pkt, MSHR* mshr)
         if (!mq.havePending()){
             cache->clearMasterRequest(Request_MSHR);
         }
-        if (mshr->originalCmd == Packet::HardPFReq) {
+        if (mshr->originalCmd == MemCmd::HardPFReq) {
             DPRINTF(HWPrefetch, "%s:Marking a HW_PF in service\n",
                     cache->name());
             //Also clear pending if need be
@@ -576,7 +571,7 @@ void
 MissQueue::handleResponse(PacketPtr &pkt, Tick time)
 {
     MSHR* mshr = (MSHR*)pkt->senderState;
-    if (((MSHR*)(pkt->senderState))->originalCmd == Packet::HardPFReq) {
+    if (((MSHR*)(pkt->senderState))->originalCmd == MemCmd::HardPFReq) {
         DPRINTF(HWPrefetch, "%s:Handling the response to a HW_PF\n",
                 cache->name());
     }
@@ -589,7 +584,7 @@ MissQueue::handleResponse(PacketPtr &pkt, Tick time)
     BlockedCause cause = NUM_BLOCKED_CAUSES;
 
     if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
-        mshr_miss_latency[mshr->originalCmd][0/*pkt->req->getThreadNum()*/] +=
+        mshr_miss_latency[mshr->originalCmd.toInt()][0/*pkt->req->getThreadNum()*/] +=
             curTick - pkt->time;
         // targets were handled in the cache tags
         if (mshr == noTargetMSHR) {
@@ -601,7 +596,7 @@ MissQueue::handleResponse(PacketPtr &pkt, Tick time)
 
         if (mshr->hasTargets()) {
             // Didn't satisfy all the targets, need to resend
-            Packet::Command cmd = mshr->getTarget()->cmd;
+            MemCmd cmd = mshr->getTarget()->cmd;
             mshr->pkt->setDest(Packet::Broadcast);
             mshr->pkt->result = Packet::Unknown;
             mq.markPending(mshr, cmd);
@@ -618,7 +613,7 @@ MissQueue::handleResponse(PacketPtr &pkt, Tick time)
         }
     } else {
         if (pkt->req->isUncacheable()) {
-            mshr_uncacheable_lat[pkt->cmd][0/*pkt->req->getThreadNum()*/] +=
+            mshr_uncacheable_lat[pkt->cmd.toInt()][0/*pkt->req->getThreadNum()*/] +=
                 curTick - pkt->time;
         }
         if (mshr->hasTargets() && pkt->req->isUncacheable()) {
@@ -713,7 +708,7 @@ MissQueue::doWriteback(Addr addr,
 {
     // Generate request
     Request * req = new Request(addr, size, 0);
-    PacketPtr pkt = new Packet(req, Packet::Writeback, -1);
+    PacketPtr pkt = new Packet(req, MemCmd::Writeback, -1);
     pkt->allocate();
     if (data) {
         memcpy(pkt->getPtr<uint8_t>(), data, size);
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index 1f9bb1e0c..d3560ff36 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -77,59 +77,59 @@ class MissQueue : public MissBuffer
      * @{
      */
     /** Number of misses that hit in the MSHRs per command and thread. */
-    Stats::Vector<> mshr_hits[NUM_MEM_CMDS];
+    Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS];
     /** Demand misses that hit in the MSHRs. */
     Stats::Formula demandMshrHits;
     /** Total number of misses that hit in the MSHRs. */
     Stats::Formula overallMshrHits;
 
     /** Number of misses that miss in the MSHRs, per command and thread. */
-    Stats::Vector<> mshr_misses[NUM_MEM_CMDS];
+    Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS];
     /** Demand misses that miss in the MSHRs. */
     Stats::Formula demandMshrMisses;
     /** Total number of misses that miss in the MSHRs. */
     Stats::Formula overallMshrMisses;
 
     /** Number of misses that miss in the MSHRs, per command and thread. */
-    Stats::Vector<> mshr_uncacheable[NUM_MEM_CMDS];
+    Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
     /** Total number of misses that miss in the MSHRs. */
     Stats::Formula overallMshrUncacheable;
 
     /** Total cycle latency of each MSHR miss, per command and thread. */
-    Stats::Vector<> mshr_miss_latency[NUM_MEM_CMDS];
+    Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
     /** Total cycle latency of demand MSHR misses. */
     Stats::Formula demandMshrMissLatency;
     /** Total cycle latency of overall MSHR misses. */
     Stats::Formula overallMshrMissLatency;
 
     /** Total cycle latency of each MSHR miss, per command and thread. */
-    Stats::Vector<> mshr_uncacheable_lat[NUM_MEM_CMDS];
+    Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
     /** Total cycle latency of overall MSHR misses. */
     Stats::Formula overallMshrUncacheableLatency;
 
     /** The total number of MSHR accesses per command and thread. */
-    Stats::Formula mshrAccesses[NUM_MEM_CMDS];
+    Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
     /** The total number of demand MSHR accesses. */
     Stats::Formula demandMshrAccesses;
     /** The total number of MSHR accesses. */
     Stats::Formula overallMshrAccesses;
 
     /** The miss rate in the MSHRs pre command and thread. */
-    Stats::Formula mshrMissRate[NUM_MEM_CMDS];
+    Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
     /** The demand miss rate in the MSHRs. */
     Stats::Formula demandMshrMissRate;
     /** The overall miss rate in the MSHRs. */
     Stats::Formula overallMshrMissRate;
 
     /** The average latency of an MSHR miss, per command and thread. */
-    Stats::Formula avgMshrMissLatency[NUM_MEM_CMDS];
+    Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
     /** The average latency of a demand MSHR miss. */
     Stats::Formula demandAvgMshrMissLatency;
     /** The average overall latency of an MSHR miss. */
     Stats::Formula overallAvgMshrMissLatency;
 
     /** The average latency of an MSHR miss, per command and thread. */
-    Stats::Formula avgMshrUncacheableLatency[NUM_MEM_CMDS];
+    Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
     /** The average overall latency of an MSHR miss. */
     Stats::Formula overallAvgMshrUncacheableLatency;
 
@@ -220,7 +220,7 @@ class MissQueue : public MissBuffer
      * @param pkt The request to update.
      * @param cmd The bus command to use.
      */
-    void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
+    void setBusCmd(PacketPtr &pkt, MemCmd cmd);
 
     /**
      * Restore the original command in case of a bus transmission error.
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index fc520b4b4..352d1ec6f 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -54,7 +54,7 @@ MSHR::MSHR()
 }
 
 void
-MSHR::allocate(Packet::Command cmd, Addr _addr, int size,
+MSHR::allocate(MemCmd cmd, Addr _addr, int size,
                PacketPtr &target)
 {
     addr = _addr;
@@ -148,7 +148,7 @@ MSHR::allocateTarget(PacketPtr &target)
      */
 
     if (!inService && target->isWrite()) {
-        pkt->cmd = Packet::WriteReq;
+        pkt->cmd = MemCmd::WriteReq;
     }
 }
 
diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh
index 281ea9d49..d0410acda 100644
--- a/src/mem/cache/miss/mshr.hh
+++ b/src/mem/cache/miss/mshr.hh
@@ -72,7 +72,7 @@ class MSHR {
     /** The number of currently allocated targets. */
     short ntargets;
     /** The original requesting command. */
-    Packet::Command originalCmd;
+    MemCmd originalCmd;
     /** Order number of assigned by the miss queue. */
     uint64_t order;
 
@@ -100,7 +100,7 @@ public:
      * @param size The number of bytes to request.
      * @param pkt  The original miss.
      */
-    void allocate(Packet::Command cmd, Addr addr, int size,
+    void allocate(MemCmd cmd, Addr addr, int size,
                   PacketPtr &pkt);
 
     /**
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index 6cb62429d..add11dfe7 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -136,7 +136,7 @@ MSHRQueue::allocateFetch(Addr addr, int size, PacketPtr &target)
     MSHR *mshr = freeList.front();
     assert(mshr->getNumTargets() == 0);
     freeList.pop_front();
-    mshr->allocate(Packet::ReadReq, addr, size, target);
+    mshr->allocate(MemCmd::ReadReq, addr, size, target);
     mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
     mshr->readyIter = pendingList.insert(pendingList.end(), mshr);
 
@@ -151,7 +151,7 @@ MSHRQueue::allocateTargetList(Addr addr, int size)
     assert(mshr->getNumTargets() == 0);
     freeList.pop_front();
     PacketPtr dummy;
-    mshr->allocate(Packet::ReadReq, addr, size, dummy);
+    mshr->allocate(MemCmd::ReadReq, addr, size, dummy);
     mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
     mshr->inService = true;
     ++inServiceMSHRs;
@@ -196,7 +196,7 @@ void
 MSHRQueue::markInService(MSHR* mshr)
 {
     //assert(mshr == pendingList.front());
-    if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq)) {
+    if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == MemCmd::UpgradeReq)) {
         assert(mshr->getNumTargets() == 0);
         deallocate(mshr);
         return;
@@ -209,7 +209,7 @@ MSHRQueue::markInService(MSHR* mshr)
 }
 
 void
-MSHRQueue::markPending(MSHR* mshr, Packet::Command cmd)
+MSHRQueue::markPending(MSHR* mshr, MemCmd cmd)
 {
     //assert(mshr->readyIter == NULL);
     mshr->pkt->cmd = cmd;
diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh
index ec2ddae8a..5069db661 100644
--- a/src/mem/cache/miss/mshr_queue.hh
+++ b/src/mem/cache/miss/mshr_queue.hh
@@ -185,7 +185,7 @@ class MSHRQueue {
      * @param mshr The MSHR to resend.
      * @param cmd The command to resend.
      */
-    void markPending(MSHR* mshr, Packet::Command cmd);
+    void markPending(MSHR* mshr, MemCmd cmd);
 
     /**
      * Squash outstanding requests with the given thread number. If a request