Backing in more changsets, getting closer to compile

base_cache.cc compiles, continuing on

src/SConscript:
    Add in compilation flags for cache files
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Back in more fixes, now base_cache compiles
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lru.cc:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/request.hh:
    Backing in more changsets, getting closer to compile

--HG--
extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed

8 files changed, 44 insertions, 48 deletions

diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index 621855c3d..912a0f5bd 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -73,7 +73,7 @@ void
 BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time)
 {
     Addr blk_addr = pkt->paddr & ~(Addr)(blk_size - 1);
-    if (pkt->cmd.isWrite() && (pkt->isUncacheable() || !writeAllocate ||
+    if (pkt->cmd.isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
                                pkt->cmd.isNoResponse())) {
         if (pkt->cmd.isNoResponse()) {
             wb.allocateAsBuffer(pkt);
@@ -93,7 +93,7 @@ BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time)
     } else {
         miss.allocate(pkt->cmd, blk_addr, pkt->req->asid, blk_size, pkt);
     }
-    if (!pkt->isUncacheable()) {
+    if (!pkt->req->isUncacheable()) {
         miss.pkt->flags |= CACHE_LINE_FILL;
     }
     cache->setBlocked(Blocked_NoMSHRs);
@@ -186,12 +186,12 @@ BlockingBuffer::handleResponse(Packet * &pkt, Tick time)
 }
 
 void
-BlockingBuffer::squash(int thread_number)
+BlockingBuffer::squash(int req->getThreadNum()ber)
 {
-    if (miss.threadNum == thread_number) {
+    if (miss.setThreadNum() == req->getThreadNum()ber) {
         Packet * target = miss.getTarget();
         miss.popTarget();
-        assert(target->thread_num == thread_number);
+        assert(target->req->setThreadNum() == req->getThreadNum()ber);
         if (target->completionEvent != NULL) {
             delete target->completionEvent;
         }
@@ -207,7 +207,7 @@ BlockingBuffer::squash(int thread_number)
 }
 
 void
-BlockingBuffer::doWriteback(Addr addr, int asid, ExecContext *xc,
+BlockingBuffer::doWriteback(Addr addr, int asid,
                             int size, uint8_t *data, bool compressed)
 {
 
@@ -224,18 +224,14 @@ BlockingBuffer::doWriteback(Addr addr, int asid, ExecContext *xc,
      * @todo Need to find a way to charge the writeback to the "correct"
      * thread.
      */
-    pkt->xc = xc;
-    if (xc)
-        pkt->thread_num = xc->getThreadNum();
-    else
-        pkt->thread_num = 0;
+    pkt->req->setThreadNum() = 0;
 
     pkt->cmd = Writeback;
     if (compressed) {
         pkt->flags |= COMPRESSED;
     }
 
-    writebacks[pkt->thread_num]++;
+    writebacks[pkt->req->getThreadNum()]++;
 
     wb.allocateAsBuffer(pkt);
     cache->setMasterRequest(Request_WB, curTick);
@@ -247,7 +243,7 @@ BlockingBuffer::doWriteback(Addr addr, int asid, ExecContext *xc,
 void
 BlockingBuffer::doWriteback(Packet * &pkt)
 {
-    writebacks[pkt->thread_num]++;
+    writebacks[pkt->req->getThreadNum()]++;
 
     wb.allocateAsBuffer(pkt);
 
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index 52256be74..08814b43e 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -164,9 +164,9 @@ public:
     /**
      * Removes all outstanding requests for a given thread number. If a request
      * has been sent to the bus, this function removes all of its targets.
-     * @param thread_number The thread number of the requests to squash.
+     * @param req->getThreadNum()ber The thread number of the requests to squash.
      */
-    void squash(int thread_number);
+    void squash(int req->getThreadNum()ber);
 
     /**
      * Return the current number of outstanding misses.
@@ -212,12 +212,11 @@ public:
      * Perform a writeback of dirty data to the given address.
      * @param addr The address to write to.
      * @param asid The address space id.
-     * @param xc The execution context of the address space.
      * @param size The number of bytes to write.
      * @param data The data to write, can be NULL.
      * @param compressed True if the data is compressed.
      */
-    void doWriteback(Addr addr, int asid, ExecContext *xc,
+    void doWriteback(Addr addr, int asid,
                      int size, uint8_t *data, bool compressed);
 
     /**
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 7902fbcee..d02f27d52 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -347,7 +347,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
 {
     MSHR* mshr = mq.allocate(pkt, size);
     mshr->order = order++;
-    if (!pkt->isUncacheable() ){//&& !pkt->isNoAllocate()) {
+    if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
         // Mark this as a cache line fill
         mshr->pkt->flags |= CACHE_LINE_FILL;
     }
@@ -399,13 +399,13 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
     int size = blkSize;
     Addr blkAddr = pkt->paddr & ~(Addr)(blkSize-1);
     MSHR* mshr = NULL;
-    if (!pkt->isUncacheable()) {
+    if (!pkt->req->isUncacheable()) {
         mshr = mq.findMatch(blkAddr, pkt->req->asid);
         if (mshr) {
             //@todo remove hw_pf here
-            mshr_hits[pkt->cmd.toIndex()][pkt->thread_num]++;
-            if (mshr->threadNum != pkt->thread_num) {
-                mshr->threadNum = -1;
+            mshr_hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+            if (mshr->getThreadNum() != pkt->req->getThreadNum()) {
+                mshr->setThreadNum() = -1;
             }
             mq.allocateTarget(mshr, pkt);
             if (mshr->pkt->isNoAllocate() && !pkt->isNoAllocate()) {
@@ -424,14 +424,14 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
             mshr_no_allocate_misses++;
         }
         else {
-            mshr_misses[pkt->cmd.toIndex()][pkt->thread_num]++;
+            mshr_misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
         }
     } else {
         //Count uncacheable accesses
-        mshr_uncacheable[pkt->cmd.toIndex()][pkt->thread_num]++;
+        mshr_uncacheable[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
         size = pkt->size;
     }
-    if (pkt->cmd.isWrite() && (pkt->isUncacheable() || !writeAllocate ||
+    if (pkt->cmd.isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
                                pkt->cmd.isNoResponse())) {
         /**
          * @todo Add write merging here.
@@ -489,7 +489,7 @@ MissQueue::getPacket()
         pkt = prefetcher->getPacket();
         if (pkt) {
             //Update statistic on number of prefetches issued (hwpf_mshr_misses)
-            mshr_misses[pkt->cmd.toIndex()][pkt->thread_num]++;
+            mshr_misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
             //It will request the bus for the future, but should clear that immedieatley
             allocateMiss(pkt, pkt->size, curTick);
             pkt = mq.getReq();
@@ -582,7 +582,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
     BlockedCause cause = NUM_BLOCKED_CAUSES;
 
     if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
-        mshr_miss_latency[mshr->originalCmd][pkt->thread_num] +=
+        mshr_miss_latency[mshr->originalCmd][pkt->req->getThreadNum()] +=
             curTick - pkt->time;
         // targets were handled in the cache tags
         if (mshr == noTargetMSHR) {
@@ -608,11 +608,11 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
             }
         }
     } else {
-        if (pkt->isUncacheable()) {
-            mshr_uncacheable_lat[pkt->cmd][pkt->thread_num] +=
+        if (pkt->req->isUncacheable()) {
+            mshr_uncacheable_lat[pkt->cmd][pkt->req->getThreadNum()] +=
                 curTick - pkt->time;
         }
-        if (mshr->hasTargets() && pkt->isUncacheable()) {
+        if (mshr->hasTargets() && pkt->req->isUncacheable()) {
             // Should only have 1 target if we had any
             assert(num_targets == 1);
             Packet * target = mshr->getTarget();
@@ -660,12 +660,12 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
 }
 
 void
-MissQueue::squash(int thread_number)
+MissQueue::squash(int req->getThreadNum()ber)
 {
     bool unblock = false;
     BlockedCause cause = NUM_BLOCKED_CAUSES;
 
-    if (noTargetMSHR && noTargetMSHR->threadNum == thread_number) {
+    if (noTargetMSHR && noTargetMSHR->setThreadNum() == req->getThreadNum()ber) {
         noTargetMSHR = NULL;
         unblock = true;
         cause = Blocked_NoTargets;
@@ -674,7 +674,7 @@ MissQueue::squash(int thread_number)
         unblock = true;
         cause = Blocked_NoMSHRs;
     }
-    mq.squash(thread_number);
+    mq.squash(req->getThreadNum()ber);
     if (!mq.havePending()) {
         cache->clearMasterRequest(Request_MSHR);
     }
@@ -704,7 +704,7 @@ MissQueue::doWriteback(Addr addr, int asid,
     Packet * pkt = buildWritebackReq(addr, asid, size, data,
                                       compressed);
 
-    writebacks[pkt->thread_num]++;
+    writebacks[pkt->req->getThreadNum()]++;
 
     allocateWrite(pkt, 0, curTick);
 }
@@ -713,7 +713,7 @@ MissQueue::doWriteback(Addr addr, int asid,
 void
 MissQueue::doWriteback(Packet * &pkt)
 {
-    writebacks[pkt->thread_num]++;
+    writebacks[pkt->req->getThreadNum()]++;
     allocateWrite(pkt, 0, curTick);
 }
 
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index ce827fe81..d45982108 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -268,9 +268,9 @@ class MissQueue
     /**
      * Removes all outstanding requests for a given thread number. If a request
      * has been sent to the bus, this function removes all of its targets.
-     * @param thread_number The thread number of the requests to squash.
+     * @param req->getThreadNum()ber The thread number of the requests to squash.
      */
-    void squash(int thread_number);
+    void squash(int req->getThreadNum()ber);
 
     /**
      * Return the current number of outstanding misses.
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 73aeaf6ca..5c3c9fd1d 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -50,7 +50,7 @@ MSHR::MSHR()
 {
     inService = false;
     ntargets = 0;
-    threadNum = -1;
+    setThreadNum() = -1;
 }
 
 void
@@ -68,7 +68,7 @@ MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
     pkt->data = new uint8_t[size];
     pkt->senderState = this;
     //Set the time here for latency calculations
-    //pkt->time = curTick;
+    pkt->time = curTick;
 
     if (target) {
         pkt->req = target->req;
@@ -85,7 +85,7 @@ MSHR::allocateAsBuffer(Packet * &target)
 {
     addr = target->paddr;
     asid = target->req->asid;
-    threadNum = target->thread_num;
+    setThreadNum() = target->req->getThreadNum();
     pkt = new Packet();
     pkt->addr = target->addr;
     pkt->dest = target->dest;
@@ -94,6 +94,7 @@ MSHR::allocateAsBuffer(Packet * &target)
     pkt->req = target->req;
     pkt->data = new uint8_t[target->size];
     pkt->senderState = this;
+    pkt->time = curTick;
 }
 
 void
@@ -161,14 +162,14 @@ MSHR::dump()
              "inService: %d thread: %d\n"
              "Addr: %x asid: %d ntargets %d\n"
              "Targets:\n",
-             inService, threadNum, addr, asid, ntargets);
+             inService, getThreadNum(), addr, asid, ntargets);
 
     TargetListIterator tar_it = targets.begin();
     for (int i = 0; i < ntargets; i++) {
         assert(tar_it != targets.end());
 
         ccprintf(cerr, "\t%d: Addr: %x cmd: %d\n",
-                 i, (*tar_it)->paddr, (*tar_it)->cmd.toIndex());
+                 i, (*tar_it)->paddr, (*tar_it)->cmdToIndex());
 
         tar_it++;
     }
diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh
index 167aa26cd..3bd6d36d1 100644
--- a/src/mem/cache/miss/mshr.hh
+++ b/src/mem/cache/miss/mshr.hh
@@ -66,7 +66,7 @@ class MSHR {
     /** True if the request has been sent to the bus. */
     bool inService;
     /** Thread number of the miss. */
-    int threadNum;
+    int getThreadNum();
     /** The request that is forwarded to the next level of the hierarchy. */
     Packet * pkt;
     /** The number of currently allocated targets. */
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index 72c8cc498..ced43d30a 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -237,18 +237,18 @@ MSHRQueue::markPending(MSHR* mshr, Packet::Command cmd)
 }
 
 void
-MSHRQueue::squash(int thread_number)
+MSHRQueue::squash(int req->getThreadNum()ber)
 {
     MSHR::Iterator i = allocatedList.begin();
     MSHR::Iterator end = allocatedList.end();
     for (; i != end;) {
         MSHR *mshr = *i;
-        if (mshr->threadNum == thread_number) {
+        if (mshr->setThreadNum() == req->getThreadNum()ber) {
             while (mshr->hasTargets()) {
                 Packet * target = mshr->getTarget();
                 mshr->popTarget();
 
-                assert(target->thread_num == thread_number);
+                assert(target->req->setThreadNum() == req->getThreadNum()ber);
                 if (target->completionEvent != NULL) {
                     delete target->completionEvent;
                 }
diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh
index 3e1d3f39f..563368d29 100644
--- a/src/mem/cache/miss/mshr_queue.hh
+++ b/src/mem/cache/miss/mshr_queue.hh
@@ -190,9 +190,9 @@ class MSHRQueue {
     /**
      * Squash outstanding requests with the given thread number. If a request
      * is in service, just squashes the targets.
-     * @param thread_number The thread to squash.
+     * @param req->getThreadNum()ber The thread to squash.
      */
-    void squash(int thread_number);
+    void squash(int req->getThreadNum()ber);
 
     /**
      * Returns true if the pending list is not empty.