Another pass of minor changes in preparation for new protocol.

src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
    Get rid of old invalidate propagation logic in preparation
    for new multilevel snoop protocol.
src/mem/cache/coherence/coherence_protocol.cc:
    L2 cache now has protocol, so protocol must handle ReadExReq
    coming in from the CPU side.
src/mem/cache/miss/mshr_queue.cc:
    Assertion is failing, so let's take it out for now.
src/mem/packet.cc:
src/mem/packet.hh:
    Add WritebackAck command.
    Reorganize enum to put responses next to corresponding requests.
    Get rid of unused WriteReqNoAck.

--HG--
extra : convert_revision : 24c519846d161978123f9aa029ae358a41546c73

1 files changed, 0 insertions, 1 deletions

diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index add11dfe7..e9aa89bf8 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -119,7 +119,6 @@ MSHRQueue::allocate(PacketPtr &pkt, int size)
     if (!pkt->needsResponse()) {
         mshr->allocateAsBuffer(pkt);
     } else {
-        assert(size !=0);
         mshr->allocate(pkt->cmd, aligned_addr, size, pkt);
         allocatedTargets += 1;
     }