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authorRon Dreslinski <rdreslin@umich.edu>2006-10-12 13:33:21 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-12 13:33:21 -0400
commitba4c224c390916fb489aa7179655c71d7fca1e13 (patch)
tree6c02f9acfeb257791c30ad995cc75a0d382e94b8 /src/mem/cache/miss
parent78aec04b660544ea7af80d76912b4422c4426602 (diff)
downloadgem5-ba4c224c390916fb489aa7179655c71d7fca1e13.tar.xz
Fix problems with unCacheable addresses in timing-coherence
src/base/traceflags.py: src/mem/physical.cc: Add debug falgs fro physical memory accesses src/mem/cache/cache_impl.hh: Snoops to uncacheable blocks should not happen src/mem/cache/miss/miss_queue.cc: Set the size properly on unCacheable accesses --HG-- extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
Diffstat (limited to 'src/mem/cache/miss')
-rw-r--r--src/mem/cache/miss/miss_queue.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index c7b0e0890..c23b542f5 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
MSHR*
MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
{
- MSHR* mshr = mq.allocate(pkt, blkSize);
+ MSHR* mshr = mq.allocate(pkt, size);
mshr->order = order++;
if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
// Mark this as a cache line fill