Still missing prefetch and tags directories as well as cache builder.

Some implementation details were left blank still, need to fill them in.

src/SConscript:
    Reorder build to compile all files first
src/mem/cache/cache.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
    More changesets pulled, now compiles everything in /miss directory and in the root directory
src/mem/packet.hh:
    Add some more support, need to clean some of it out once everything is working

--HG--
extra : convert_revision : ba73676165810edf2c2effaf5fbad8397d6bd800

5 files changed, 165 insertions, 156 deletions

diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index 912a0f5bd..d745cb8c6 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -33,12 +33,12 @@
  * Definitions of a simple buffer for a blocking cache.
  */
 
-#include "cpu/exec_context.hh"
 #include "cpu/smt.hh" //for maxThreadsPerCPU
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/miss/blocking_buffer.hh"
 #include "mem/cache/prefetch/base_prefetcher.hh"
 #include "sim/eventq.hh" // for Event declaration.
+#include "mem/request.hh"
 
 using namespace TheISA;
 
@@ -72,26 +72,26 @@ BlockingBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
 void
 BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time)
 {
-    Addr blk_addr = pkt->paddr & ~(Addr)(blk_size - 1);
-    if (pkt->cmd.isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
-                               pkt->cmd.isNoResponse())) {
-        if (pkt->cmd.isNoResponse()) {
+    Addr blk_addr = pkt->getAddr() & ~(Addr)(blk_size - 1);
+    if (pkt->isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
+                               !pkt->needsResponse())) {
+        if (!pkt->needsResponse()) {
             wb.allocateAsBuffer(pkt);
         } else {
-            wb.allocate(pkt->cmd, blk_addr, pkt->req->asid, blk_size, pkt);
-        }
-        if (cache->doData()) {
-            memcpy(wb.pkt->data, pkt->data, blk_size);
+            wb.allocate(pkt->cmd, blk_addr, pkt->req->getAsid(), blk_size, pkt);
         }
+
+        memcpy(wb.pkt->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(), blk_size);
+
         cache->setBlocked(Blocked_NoWBBuffers);
         cache->setMasterRequest(Request_WB, time);
         return;
     }
 
-    if (pkt->cmd.isNoResponse()) {
+    if (!pkt->needsResponse()) {
         miss.allocateAsBuffer(pkt);
     } else {
-        miss.allocate(pkt->cmd, blk_addr, pkt->req->asid, blk_size, pkt);
+        miss.allocate(pkt->cmd, blk_addr, pkt->req->getAsid(), blk_size, pkt);
     }
     if (!pkt->req->isUncacheable()) {
         miss.pkt->flags |= CACHE_LINE_FILL;
@@ -112,27 +112,27 @@ BlockingBuffer::getPacket()
 void
 BlockingBuffer::setBusCmd(Packet * &pkt, Packet::Command cmd)
 {
-    MSHR *mshr = pkt->senderState;
+    MSHR *mshr = (MSHR*) pkt->senderState;
     mshr->originalCmd = pkt->cmd;
     if (pkt->isCacheFill())
-        pkt->cmd = cmd;
+        pkt->cmdOverride(cmd);
 }
 
 void
 BlockingBuffer::restoreOrigCmd(Packet * &pkt)
 {
-    pkt->cmd = pkt->senderState->originalCmd;
+    pkt->cmdOverride(((MSHR*)(pkt->senderState))->originalCmd);
 }
 
 void
 BlockingBuffer::markInService(Packet * &pkt)
 {
-    if (!pkt->isCacheFill() && pkt->cmd.isWrite()) {
+    if (!pkt->isCacheFill() && pkt->isWrite()) {
         // Forwarding a write/ writeback, don't need to change
         // the command
-        assert(pkt->senderState == &wb);
+        assert((MSHR*)pkt->senderState == &wb);
         cache->clearMasterRequest(Request_WB);
-        if (pkt->cmd.isNoResponse()) {
+        if (!pkt->needsResponse()) {
             assert(wb.getNumTargets() == 0);
             wb.deallocate();
             cache->clearBlocked(Blocked_NoWBBuffers);
@@ -140,9 +140,9 @@ BlockingBuffer::markInService(Packet * &pkt)
             wb.inService = true;
         }
     } else {
-        assert(pkt->senderState == &miss);
+        assert((MSHR*)pkt->senderState == &miss);
         cache->clearMasterRequest(Request_MSHR);
-        if (pkt->cmd.isNoResponse()) {
+        if (!pkt->needsResponse()) {
             assert(miss.getNumTargets() == 0);
             miss.deallocate();
             cache->clearBlocked(Blocked_NoMSHRs);
@@ -158,24 +158,24 @@ BlockingBuffer::handleResponse(Packet * &pkt, Tick time)
 {
     if (pkt->isCacheFill()) {
         // targets were handled in the cache tags
-        assert(pkt->senderState == &miss);
+        assert((MSHR*)pkt->senderState == &miss);
         miss.deallocate();
         cache->clearBlocked(Blocked_NoMSHRs);
     } else {
-        if (pkt->senderState->hasTargets()) {
+        if (((MSHR*)(pkt->senderState))->hasTargets()) {
             // Should only have 1 target if we had any
-            assert(pkt->senderState->getNumTargets() == 1);
-            Packet * target = pkt->senderState->getTarget();
-            pkt->senderState->popTarget();
-            if (cache->doData() && pkt->cmd.isRead()) {
-                memcpy(target->data, pkt->data, target->size);
+            assert(((MSHR*)(pkt->senderState))->getNumTargets() == 1);
+            Packet * target = ((MSHR*)(pkt->senderState))->getTarget();
+            ((MSHR*)(pkt->senderState))->popTarget();
+            if (pkt->isRead()) {
+                memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(), target->getSize());
             }
             cache->respond(target, time);
-            assert(!pkt->senderState->hasTargets());
+            assert(!((MSHR*)(pkt->senderState))->hasTargets());
         }
 
-        if (pkt->cmd.isWrite()) {
-            assert(pkt->senderState == &wb);
+        if (pkt->isWrite()) {
+            assert(((MSHR*)(pkt->senderState)) == &wb);
             wb.deallocate();
             cache->clearBlocked(Blocked_NoWBBuffers);
         } else {
@@ -186,15 +186,12 @@ BlockingBuffer::handleResponse(Packet * &pkt, Tick time)
 }
 
 void
-BlockingBuffer::squash(int req->getThreadNum()ber)
+BlockingBuffer::squash(int threadNum)
 {
-    if (miss.setThreadNum() == req->getThreadNum()ber) {
+    if (miss.threadNum == threadNum) {
         Packet * target = miss.getTarget();
         miss.popTarget();
-        assert(target->req->setThreadNum() == req->getThreadNum()ber);
-        if (target->completionEvent != NULL) {
-            delete target->completionEvent;
-        }
+        assert(target->req->getThreadNum() == threadNum);
         target = NULL;
         assert(!miss.hasTargets());
         miss.ntargets=0;
@@ -210,27 +207,20 @@ void
 BlockingBuffer::doWriteback(Addr addr, int asid,
                             int size, uint8_t *data, bool compressed)
 {
-
     // Generate request
-    Packet * pkt = new Packet();
-    pkt->paddr = addr;
-    pkt->req->asid = asid;
-    pkt->size = size;
-    pkt->data = new uint8_t[size];
+    Request * req = new Request(addr, size, 0);
+    Packet * pkt = new Packet(req, Packet::Writeback, -1);
+    uint8_t *new_data = new uint8_t[size];
+    pkt->dataDynamicArray<uint8_t>(new_data);
     if (data) {
-        memcpy(pkt->data, data, size);
+        memcpy(pkt->getPtr<uint8_t>(), data, size);
     }
-    /**
-     * @todo Need to find a way to charge the writeback to the "correct"
-     * thread.
-     */
-    pkt->req->setThreadNum() = 0;
 
-    pkt->cmd = Writeback;
     if (compressed) {
         pkt->flags |= COMPRESSED;
     }
 
+    ///All writebacks charged to same thread @todo figure this out
     writebacks[pkt->req->getThreadNum()]++;
 
     wb.allocateAsBuffer(pkt);
@@ -249,9 +239,8 @@ BlockingBuffer::doWriteback(Packet * &pkt)
 
     // Since allocate as buffer copies the request,
     // need to copy data here.
-    if (cache->doData()) {
-        memcpy(wb.pkt->data, pkt->data, pkt->size);
-    }
+        memcpy(wb.pkt->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(), pkt->getSize());
+
     cache->setBlocked(Blocked_NoWBBuffers);
     cache->setMasterRequest(Request_WB, curTick);
 }
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index d02f27d52..34290351d 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -34,7 +34,6 @@
  * Miss and writeback queue definitions.
  */
 
-#include "cpu/exec_context.hh"
 #include "cpu/smt.hh" //for maxThreadsPerCPU
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/miss/miss_queue.hh"
@@ -59,6 +58,10 @@ MissQueue::MissQueue(int numMSHRs, int numTargets, int write_buffers,
 void
 MissQueue::regStats(const string &name)
 {
+    Request temp_req;
+    Packet::Command temp_cmd = Packet::ReadReq;
+    Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
+
     using namespace Stats;
 
     writebacks
@@ -71,7 +74,7 @@ MissQueue::regStats(const string &name)
     // MSHR hit statistics
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
         Packet::Command cmd = (Packet::Command)access_idx;
-        const string &cstr = cmd.toString();
+        const string &cstr = temp_pkt.cmdIdxToString(cmd);
 
         mshr_hits[access_idx]
             .init(maxThreadsPerCPU)
@@ -86,20 +89,20 @@ MissQueue::regStats(const string &name)
         .desc("number of demand (read+write) MSHR hits")
         .flags(total)
         ;
-    demandMshrHits = mshr_hits[Read] + mshr_hits[Write];
+    demandMshrHits = mshr_hits[Packet::ReadReq] + mshr_hits[Packet::WriteReq];
 
     overallMshrHits
         .name(name + ".overall_mshr_hits")
         .desc("number of overall MSHR hits")
         .flags(total)
         ;
-    overallMshrHits = demandMshrHits + mshr_hits[Soft_Prefetch] +
-        mshr_hits[Hard_Prefetch];
+    overallMshrHits = demandMshrHits + mshr_hits[Packet::SoftPFReq] +
+        mshr_hits[Packet::HardPFReq];
 
     // MSHR miss statistics
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::CommandEnum)access_idx;
-        const string &cstr = cmd.toString();
+        Packet::Command cmd = (Packet::Command)access_idx;
+        const string &cstr = temp_pkt.cmdIdxToString(cmd);
 
         mshr_misses[access_idx]
             .init(maxThreadsPerCPU)
@@ -114,20 +117,20 @@ MissQueue::regStats(const string &name)
         .desc("number of demand (read+write) MSHR misses")
         .flags(total)
         ;
-    demandMshrMisses = mshr_misses[Read] + mshr_misses[Write];
+    demandMshrMisses = mshr_misses[Packet::ReadReq] + mshr_misses[Packet::WriteReq];
 
     overallMshrMisses
         .name(name + ".overall_mshr_misses")
         .desc("number of overall MSHR misses")
         .flags(total)
         ;
-    overallMshrMisses = demandMshrMisses + mshr_misses[Soft_Prefetch] +
-        mshr_misses[Hard_Prefetch];
+    overallMshrMisses = demandMshrMisses + mshr_misses[Packet::SoftPFReq] +
+        mshr_misses[Packet::HardPFReq];
 
     // MSHR miss latency statistics
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::CommandEnum)access_idx;
-        const string &cstr = cmd.toString();
+        Packet::Command cmd = (Packet::Command)access_idx;
+        const string &cstr = temp_pkt.cmdIdxToString(cmd);
 
         mshr_miss_latency[access_idx]
             .init(maxThreadsPerCPU)
@@ -142,7 +145,8 @@ MissQueue::regStats(const string &name)
         .desc("number of demand (read+write) MSHR miss cycles")
         .flags(total)
         ;
-    demandMshrMissLatency = mshr_miss_latency[Read] + mshr_miss_latency[Write];
+    demandMshrMissLatency = mshr_miss_latency[Packet::ReadReq]
+        + mshr_miss_latency[Packet::WriteReq];
 
     overallMshrMissLatency
         .name(name + ".overall_mshr_miss_latency")
@@ -150,12 +154,12 @@ MissQueue::regStats(const string &name)
         .flags(total)
         ;
     overallMshrMissLatency = demandMshrMissLatency +
-        mshr_miss_latency[Soft_Prefetch] + mshr_miss_latency[Hard_Prefetch];
+        mshr_miss_latency[Packet::SoftPFReq] + mshr_miss_latency[Packet::HardPFReq];
 
     // MSHR uncacheable statistics
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::CommandEnum)access_idx;
-        const string &cstr = cmd.toString();
+        Packet::Command cmd = (Packet::Command)access_idx;
+        const string &cstr = temp_pkt.cmdIdxToString(cmd);
 
         mshr_uncacheable[access_idx]
             .init(maxThreadsPerCPU)
@@ -170,13 +174,14 @@ MissQueue::regStats(const string &name)
         .desc("number of overall MSHR uncacheable misses")
         .flags(total)
         ;
-    overallMshrUncacheable = mshr_uncacheable[Read] + mshr_uncacheable[Write]
-        + mshr_uncacheable[Soft_Prefetch] + mshr_uncacheable[Hard_Prefetch];
+    overallMshrUncacheable = mshr_uncacheable[Packet::ReadReq]
+        + mshr_uncacheable[Packet::WriteReq] + mshr_uncacheable[Packet::SoftPFReq]
+        + mshr_uncacheable[Packet::HardPFReq];
 
     // MSHR miss latency statistics
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::CommandEnum)access_idx;
-        const string &cstr = cmd.toString();
+        Packet::Command cmd = (Packet::Command)access_idx;
+        const string &cstr = temp_pkt.cmdIdxToString(cmd);
 
         mshr_uncacheable_lat[access_idx]
             .init(maxThreadsPerCPU)
@@ -191,15 +196,16 @@ MissQueue::regStats(const string &name)
         .desc("number of overall MSHR uncacheable cycles")
         .flags(total)
         ;
-    overallMshrUncacheableLatency = mshr_uncacheable_lat[Read]
-        + mshr_uncacheable_lat[Write] + mshr_uncacheable_lat[Soft_Prefetch]
-        + mshr_uncacheable_lat[Hard_Prefetch];
+    overallMshrUncacheableLatency = mshr_uncacheable_lat[Packet::ReadReq]
+        + mshr_uncacheable_lat[Packet::WriteReq]
+        + mshr_uncacheable_lat[Packet::SoftPFReq]
+        + mshr_uncacheable_lat[Packet::HardPFReq];
 
 #if 0
     // MSHR access formulas
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::CommandEnum)access_idx;
-        const string &cstr = cmd.toString();
+        Packet::Command cmd = (Packet::Command)access_idx;
+        const string &cstr = temp_pkt.cmdIdxToString(cmd);
 
         mshrAccesses[access_idx]
             .name(name + "." + cstr + "_mshr_accesses")
@@ -229,8 +235,8 @@ MissQueue::regStats(const string &name)
 
     // MSHR miss rate formulas
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::CommandEnum)access_idx;
-        const string &cstr = cmd.toString();
+        Packet::Command cmd = (Packet::Command)access_idx;
+        const string &cstr = temp_pkt.cmdIdxToString(cmd);
 
         mshrMissRate[access_idx]
             .name(name + "." + cstr + "_mshr_miss_rate")
@@ -258,8 +264,8 @@ MissQueue::regStats(const string &name)
 
     // mshrMiss latency formulas
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::CommandEnum)access_idx;
-        const string &cstr = cmd.toString();
+        Packet::Command cmd = (Packet::Command)access_idx;
+        const string &cstr = temp_pkt.cmdIdxToString(cmd);
 
         avgMshrMissLatency[access_idx]
             .name(name + "." + cstr + "_avg_mshr_miss_latency")
@@ -287,8 +293,8 @@ MissQueue::regStats(const string &name)
 
     // mshrUncacheable latency formulas
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
-        Packet::Command cmd = (Packet::CommandEnum)access_idx;
-        const string &cstr = cmd.toString();
+        Packet::Command cmd = (Packet::Command)access_idx;
+        const string &cstr = temp_pkt.cmdIdxToString(cmd);
 
         avgMshrUncacheableLatency[access_idx]
             .name(name + "." + cstr + "_avg_mshr_uncacheable_latency")
@@ -354,7 +360,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
     if (mq.isFull()) {
         cache->setBlocked(Blocked_NoMSHRs);
     }
-    if (pkt->cmd != Hard_Prefetch) {
+    if (pkt->cmd != Packet::HardPFReq) {
         //If we need to request the bus (not on HW prefetch), do so
         cache->setMasterRequest(Request_MSHR, time);
     }
@@ -365,18 +371,21 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
 MSHR*
 MissQueue::allocateWrite(Packet * &pkt, int size, Tick time)
 {
-    MSHR* mshr = wb.allocate(pkt,pkt->size);
+    MSHR* mshr = wb.allocate(pkt,pkt->getSize());
     mshr->order = order++;
-    if (cache->doData()){
-        if (pkt->isCompressed()) {
-            delete [] mshr->pkt->data;
-            mshr->pkt->actualSize = pkt->actualSize;
-            mshr->pkt->data = new uint8_t[pkt->actualSize];
-            memcpy(mshr->pkt->data, pkt->data, pkt->actualSize);
-        } else {
-            memcpy(mshr->pkt->data, pkt->data, pkt->size);
-        }
-    }
+
+//REMOVING COMPRESSION FOR NOW
+#if 0
+    if (pkt->isCompressed()) {
+        mshr->pkt->deleteData();
+        mshr->pkt->actualSize = pkt->actualSize;
+        mshr->pkt->data = new uint8_t[pkt->actualSize];
+        memcpy(mshr->pkt->data, pkt->data, pkt->actualSize);
+    } else {
+#endif
+        memcpy(mshr->pkt->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(), pkt->getSize());
+  //{
+
     if (wb.isFull()) {
         cache->setBlocked(Blocked_NoWBBuffers);
     }
@@ -397,15 +406,15 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
     if (prefetchMiss) prefetcher->handleMiss(pkt, time);
 
     int size = blkSize;
-    Addr blkAddr = pkt->paddr & ~(Addr)(blkSize-1);
+    Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);
     MSHR* mshr = NULL;
     if (!pkt->req->isUncacheable()) {
-        mshr = mq.findMatch(blkAddr, pkt->req->asid);
+        mshr = mq.findMatch(blkAddr, pkt->req->getAsid());
         if (mshr) {
             //@todo remove hw_pf here
             mshr_hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
-            if (mshr->getThreadNum() != pkt->req->getThreadNum()) {
-                mshr->setThreadNum() = -1;
+            if (mshr->threadNum != pkt->req->getThreadNum()) {
+                mshr->threadNum = -1;
             }
             mq.allocateTarget(mshr, pkt);
             if (mshr->pkt->isNoAllocate() && !pkt->isNoAllocate()) {
@@ -429,14 +438,14 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
     } else {
         //Count uncacheable accesses
         mshr_uncacheable[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
-        size = pkt->size;
+        size = pkt->getSize();
     }
-    if (pkt->cmd.isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
-                               pkt->cmd.isNoResponse())) {
+    if (pkt->isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
+                               !pkt->needsResponse())) {
         /**
          * @todo Add write merging here.
          */
-        mshr = allocateWrite(pkt, pkt->size, time);
+        mshr = allocateWrite(pkt, pkt->getSize(), time);
         return;
     }
 
@@ -468,7 +477,7 @@ MissQueue::getPacket()
         pkt = wb.getReq();
         // Need to search for earlier miss.
         MSHR *mshr = mq.findPending(pkt);
-        if (mshr && mshr->order < pkt->senderState->order) {
+        if (mshr && mshr->order < ((MSHR*)(pkt->senderState))->order) {
             // Service misses in order until conflict is cleared.
             return mq.getReq();
         }
@@ -491,7 +500,7 @@ MissQueue::getPacket()
             //Update statistic on number of prefetches issued (hwpf_mshr_misses)
             mshr_misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
             //It will request the bus for the future, but should clear that immedieatley
-            allocateMiss(pkt, pkt->size, curTick);
+            allocateMiss(pkt, pkt->getSize(), curTick);
             pkt = mq.getReq();
             assert(pkt); //We should get back a req b/c we just put one in
         }
@@ -503,7 +512,7 @@ void
 MissQueue::setBusCmd(Packet * &pkt, Packet::Command cmd)
 {
     assert(pkt->senderState != 0);
-    MSHR * mshr = pkt->senderState;
+    MSHR * mshr = (MSHR*)pkt->senderState;
     mshr->originalCmd = pkt->cmd;
     if (pkt->isCacheFill() || pkt->isNoAllocate())
         pkt->cmd = cmd;
@@ -512,7 +521,7 @@ MissQueue::setBusCmd(Packet * &pkt, Packet::Command cmd)
 void
 MissQueue::restoreOrigCmd(Packet * &pkt)
 {
-    pkt->cmd = pkt->senderState->originalCmd;
+    pkt->cmd = ((MSHR*)(pkt->senderState))->originalCmd;
 }
 
 void
@@ -526,11 +535,11 @@ MissQueue::markInService(Packet * &pkt)
      * @todo Should include MSHRQueue pointer in MSHR to select the correct
      * one.
      */
-    if ((!pkt->isCacheFill() && pkt->cmd.isWrite()) || pkt->cmd == Copy) {
+    if ((!pkt->isCacheFill() && pkt->isWrite())) {
         // Forwarding a write/ writeback, don't need to change
         // the command
         unblock = wb.isFull();
-        wb.markInService(pkt->senderState);
+        wb.markInService((MSHR*)pkt->senderState);
         if (!wb.havePending()){
             cache->clearMasterRequest(Request_WB);
         }
@@ -541,11 +550,11 @@ MissQueue::markInService(Packet * &pkt)
         }
     } else {
         unblock = mq.isFull();
-        mq.markInService(pkt->senderState);
+        mq.markInService((MSHR*)pkt->senderState);
         if (!mq.havePending()){
             cache->clearMasterRequest(Request_MSHR);
         }
-        if (pkt->senderState->originalCmd == Hard_Prefetch) {
+        if (((MSHR*)(pkt->senderState))->originalCmd == Packet::HardPFReq) {
             DPRINTF(HWPrefetch, "%s:Marking a HW_PF in service\n",
                     cache->name());
             //Also clear pending if need be
@@ -568,8 +577,8 @@ MissQueue::markInService(Packet * &pkt)
 void
 MissQueue::handleResponse(Packet * &pkt, Tick time)
 {
-    MSHR* mshr = pkt->senderState;
-    if (pkt->senderState->originalCmd == Hard_Prefetch) {
+    MSHR* mshr = (MSHR*)pkt->senderState;
+    if (((MSHR*)(pkt->senderState))->originalCmd == Packet::HardPFReq) {
         DPRINTF(HWPrefetch, "%s:Handling the response to a HW_PF\n",
                 cache->name());
     }
@@ -617,8 +626,9 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
             assert(num_targets == 1);
             Packet * target = mshr->getTarget();
             mshr->popTarget();
-            if (cache->doData() && pkt->cmd.isRead()) {
-                memcpy(target->data, pkt->data, target->size);
+            if (pkt->isRead()) {
+                memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(),
+                       target->getSize());
             }
             cache->respond(target, time);
             assert(!mshr->hasTargets());
@@ -629,14 +639,15 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
             while (mshr->hasTargets()) {
                 Packet * target = mshr->getTarget();
                 mshr->popTarget();
-                if (cache->doData() && pkt->cmd.isRead()) {
-                    memcpy(target->data, pkt->data, target->size);
+                if (pkt->isRead()) {
+                    memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(),
+                           target->getSize());
                 }
                 cache->respond(target, time);
             }
         }
 
-        if (pkt->cmd.isWrite()) {
+        if (pkt->isWrite()) {
             // If the wrtie buffer is full, we might unblock now
             unblock = wb.isFull();
             wb.deallocate(mshr);
@@ -660,12 +671,12 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
 }
 
 void
-MissQueue::squash(int req->getThreadNum()ber)
+MissQueue::squash(int threadNum)
 {
     bool unblock = false;
     BlockedCause cause = NUM_BLOCKED_CAUSES;
 
-    if (noTargetMSHR && noTargetMSHR->setThreadNum() == req->getThreadNum()ber) {
+    if (noTargetMSHR && noTargetMSHR->threadNum == threadNum) {
         noTargetMSHR = NULL;
         unblock = true;
         cause = Blocked_NoTargets;
@@ -674,7 +685,7 @@ MissQueue::squash(int req->getThreadNum()ber)
         unblock = true;
         cause = Blocked_NoMSHRs;
     }
-    mq.squash(req->getThreadNum()ber);
+    mq.squash(threadNum);
     if (!mq.havePending()) {
         cache->clearMasterRequest(Request_MSHR);
     }
@@ -701,9 +712,19 @@ MissQueue::doWriteback(Addr addr, int asid,
                        int size, uint8_t *data, bool compressed)
 {
     // Generate request
-    Packet * pkt = buildWritebackReq(addr, asid, size, data,
-                                      compressed);
+    Request * req = new Request(addr, size, 0);
+    Packet * pkt = new Packet(req, Packet::Writeback, -1);
+    uint8_t *new_data = new uint8_t[size];
+    pkt->dataDynamicArray<uint8_t>(new_data);
+    if (data) {
+        memcpy(pkt->getPtr<uint8_t>(), data, size);
+    }
+
+    if (compressed) {
+        pkt->flags |= COMPRESSED;
+    }
 
+    ///All writebacks charged to same thread @todo figure this out
     writebacks[pkt->req->getThreadNum()]++;
 
     allocateWrite(pkt, 0, curTick);
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 5c3c9fd1d..fe8cbeea4 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -50,13 +50,15 @@ MSHR::MSHR()
 {
     inService = false;
     ntargets = 0;
-    setThreadNum() = -1;
+    threadNum = -1;
 }
 
 void
 MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
                Packet * &target)
 {
+    assert("NEED TO FIX YET\n" && 0);
+#if 0
     assert(targets.empty());
     addr = _addr;
     asid = _asid;
@@ -74,6 +76,7 @@ MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
         pkt->req = target->req;
         allocateTarget(target);
     }
+#endif
 }
 
 // Since we aren't sure if data is being used, don't copy here.
@@ -83,17 +86,13 @@ MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
 void
 MSHR::allocateAsBuffer(Packet * &target)
 {
-    addr = target->paddr;
-    asid = target->req->asid;
-    setThreadNum() = target->req->getThreadNum();
-    pkt = new Packet();
-    pkt->addr = target->addr;
-    pkt->dest = target->dest;
-    pkt->cmd = target->cmd;
-    pkt->size = target->size;
-    pkt->req = target->req;
-    pkt->data = new uint8_t[target->size];
-    pkt->senderState = this;
+    addr = target->getAddr();
+    asid = target->req->getAsid();
+    threadNum = target->req->getThreadNum();
+    pkt = new Packet(target->req, target->cmd, -1);
+    uint8_t *new_data = new uint8_t[target->getSize()];
+    pkt->dataDynamicArray<uint8_t>(new_data);
+    pkt->senderState = (Packet::SenderState*)this;
     pkt->time = curTick;
 }
 
@@ -117,11 +116,11 @@ MSHR::allocateTarget(Packet * &target)
     //If we append an invalidate and we issued a read to the bus,
     //but now have some pending writes, we need to move
     //the invalidate to before the first non-read
-    if (inService && pkt->cmd.isRead() && target->cmd.isInvalidate()) {
+    if (inService && pkt->isRead() && target->isInvalidate()) {
         std::list<Packet *> temp;
 
         while (!targets.empty()) {
-            if (!targets.front()->cmd.isRead()) break;
+            if (!targets.front()->isRead()) break;
             //Place on top of temp stack
             temp.push_front(targets.front());
             //Remove from targets
@@ -148,8 +147,8 @@ MSHR::allocateTarget(Packet * &target)
      * @todo really prioritize the target commands.
      */
 
-    if (!inService && target->cmd.isWrite()) {
-        pkt->cmd = WriteReq;
+    if (!inService && target->isWrite()) {
+        pkt->cmd = Packet::WriteReq;
     }
 }
 
@@ -162,14 +161,14 @@ MSHR::dump()
              "inService: %d thread: %d\n"
              "Addr: %x asid: %d ntargets %d\n"
              "Targets:\n",
-             inService, getThreadNum(), addr, asid, ntargets);
+             inService, threadNum, addr, asid, ntargets);
 
     TargetListIterator tar_it = targets.begin();
     for (int i = 0; i < ntargets; i++) {
         assert(tar_it != targets.end());
 
         ccprintf(cerr, "\t%d: Addr: %x cmd: %d\n",
-                 i, (*tar_it)->paddr, (*tar_it)->cmdToIndex());
+                 i, (*tar_it)->getAddr(), (*tar_it)->cmdToIndex());
 
         tar_it++;
     }
diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh
index 3bd6d36d1..167aa26cd 100644
--- a/src/mem/cache/miss/mshr.hh
+++ b/src/mem/cache/miss/mshr.hh
@@ -66,7 +66,7 @@ class MSHR {
     /** True if the request has been sent to the bus. */
     bool inService;
     /** Thread number of the miss. */
-    int getThreadNum();
+    int threadNum;
     /** The request that is forwarded to the next level of the hierarchy. */
     Packet * pkt;
     /** The number of currently allocated targets. */
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index ced43d30a..6516a99f8 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -94,17 +94,19 @@ MSHRQueue::findPending(Packet * &pkt) const
     MSHR::ConstIterator end = pendingList.end();
     for (; i != end; ++i) {
         MSHR *mshr = *i;
-        if (mshr->addr < pkt->addr) {
-            if (mshr->addr + mshr->pkt->size > pkt->addr) {
+        if (mshr->addr < pkt->getAddr()) {
+            if (mshr->addr + mshr->pkt->getSize() > pkt->getAddr()) {
                 return mshr;
             }
         } else {
-            if (pkt->addr + pkt->size > mshr->addr) {
+            if (pkt->getAddr() + pkt->getSize() > mshr->addr) {
                 return mshr;
             }
         }
 
         //need to check destination address for copies.
+        //TEMP NOT DOING COPIES
+#if 0
         if (mshr->pkt->cmd == Copy) {
             Addr dest = mshr->pkt->dest;
             if (dest < pkt->addr) {
@@ -117,6 +119,7 @@ MSHRQueue::findPending(Packet * &pkt) const
                 }
             }
         }
+#endif
     }
     return NULL;
 }
@@ -124,16 +127,16 @@ MSHRQueue::findPending(Packet * &pkt) const
 MSHR*
 MSHRQueue::allocate(Packet * &pkt, int size)
 {
-    Addr aligned_addr = pkt->addr & ~((Addr)size - 1);
+    Addr aligned_addr = pkt->getAddr() & ~((Addr)size - 1);
     MSHR *mshr = freeList.front();
     assert(mshr->getNumTargets() == 0);
     freeList.pop_front();
 
-    if (pkt->cmd.isNoResponse()) {
+    if (!pkt->needsResponse()) {
         mshr->allocateAsBuffer(pkt);
     } else {
         assert(size !=0);
-        mshr->allocate(pkt->cmd, aligned_addr, pkt->req->req->asid, size, pkt);
+        mshr->allocate(pkt->cmd, aligned_addr, pkt->req->getAsid(), size, pkt);
         allocatedTargets += 1;
     }
     mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
@@ -149,7 +152,7 @@ MSHRQueue::allocateFetch(Addr addr, int asid, int size, Packet * &target)
     MSHR *mshr = freeList.front();
     assert(mshr->getNumTargets() == 0);
     freeList.pop_front();
-    mshr->allocate(Read, addr, asid, size, target);
+    mshr->allocate(Packet::ReadReq, addr, asid, size, target);
     mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
     mshr->readyIter = pendingList.insert(pendingList.end(), mshr);
 
@@ -164,7 +167,7 @@ MSHRQueue::allocateTargetList(Addr addr, int asid, int size)
     assert(mshr->getNumTargets() == 0);
     freeList.pop_front();
     Packet * dummy;
-    mshr->allocate(Read, addr, asid, size, dummy);
+    mshr->allocate(Packet::ReadReq, addr, asid, size, dummy);
     mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
     mshr->inService = true;
     ++inServiceMSHRs;
@@ -209,7 +212,7 @@ void
 MSHRQueue::markInService(MSHR* mshr)
 {
     //assert(mshr == pendingList.front());
-    if (mshr->pkt->cmd.isNoResponse()) {
+    if (!mshr->pkt->needsResponse()) {
         assert(mshr->getNumTargets() == 0);
         deallocate(mshr);
         return;
@@ -237,21 +240,18 @@ MSHRQueue::markPending(MSHR* mshr, Packet::Command cmd)
 }
 
 void
-MSHRQueue::squash(int req->getThreadNum()ber)
+MSHRQueue::squash(int threadNum)
 {
     MSHR::Iterator i = allocatedList.begin();
     MSHR::Iterator end = allocatedList.end();
     for (; i != end;) {
         MSHR *mshr = *i;
-        if (mshr->setThreadNum() == req->getThreadNum()ber) {
+        if (mshr->threadNum == threadNum) {
             while (mshr->hasTargets()) {
                 Packet * target = mshr->getTarget();
                 mshr->popTarget();
 
-                assert(target->req->setThreadNum() == req->getThreadNum()ber);
-                if (target->completionEvent != NULL) {
-                    delete target->completionEvent;
-                }
+                assert(target->req->getThreadNum() == threadNum);
                 target = NULL;
             }
             assert(!mshr->hasTargets());