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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-07 11:36:55 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-07 11:36:55 -0400 |
| commit | 178d114fa5ed5927a2665a30ae5813ea2e2fbfea (patch) | |
| tree | b454e47361124b4de94dab9cda71ffce74b08d0a /src/mem/cache/miss | |
| parent | c42a7bc4f6c03703e17fb55afe5ba8e2d920e5d5 (diff) | |
| download | gem5-178d114fa5ed5927a2665a30ae5813ea2e2fbfea.tar.xz | |
Fix infinite writebacks bug in cache.
src/mem/cache/cache_impl.hh:
Make sure to pop the list. Fixes infinite writeback bug.
src/mem/cache/miss/mshr_queue.cc:
Add an assert as sanity check in case .full() stops working again.
--HG--
extra : convert_revision : d847e49a397eeb0b7c5ac060fcfc3eaeac921311
Diffstat (limited to 'src/mem/cache/miss')
| -rw-r--r-- | src/mem/cache/miss/mshr_queue.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index e54f7aa08..bd9667529 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -128,6 +128,7 @@ MSHR* MSHRQueue::allocate(Packet * &pkt, int size) { Addr aligned_addr = pkt->getAddr() & ~((Addr)size - 1); + assert(!freeList.empty()); MSHR *mshr = freeList.front(); assert(mshr->getNumTargets() == 0); freeList.pop_front(); |