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authorRon Dreslinski <rdreslin@umich.edu>2006-10-17 16:47:22 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-17 16:47:22 -0400
commit4fff6d460311d77e0056a546df41366d5a3b4604 (patch)
treee53419f2e4c6c38ff874e144d22fabeb9f637e6d /src/mem/cache/miss
parent6e8bfa4e63cd09b065b77166577104c06636b6f3 (diff)
downloadgem5-4fff6d460311d77e0056a546df41366d5a3b4604.tar.xz
Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request.
Still need to rework upgrades into this system, but works for now. src/mem/cache/base_cache.cc: Re order code to be more readable src/mem/cache/base_cache.hh: Be sure to delete the copy on a bus block src/mem/cache/cache_impl.hh: Be sure to remove the copy on a writeback success src/mem/cache/miss/mshr_queue.cc: Demorgans to make it easier to understand src/mem/tport.cc: Delete writebacks --HG-- extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
Diffstat (limited to 'src/mem/cache/miss')
-rw-r--r--src/mem/cache/miss/mshr_queue.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index 1876a8987..9d2a692cf 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -213,7 +213,7 @@ void
MSHRQueue::markInService(MSHR* mshr)
{
//assert(mshr == pendingList.front());
- if (!(mshr->pkt->needsResponse() || mshr->pkt->cmd == Packet::UpgradeReq)) {
+ if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq)) {
assert(mshr->getNumTargets() == 0);
if ((mshr->pkt->flags & SATISFIED) && (mshr->pkt->cmd == Packet::Writeback)) {
//Writeback hit, so delete it