Turn cache MissQueue/BlockingBuffer into virtual object

instead of template parameter.

--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0

6 files changed, 328 insertions, 124 deletions

diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index bf741e547..4a431d82d 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -33,11 +33,9 @@
  * Definitions of a simple buffer for a blocking cache.
  */
 
-#include "cpu/smt.hh" //for maxThreadsPerCPU
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/miss/blocking_buffer.hh"
 #include "mem/cache/prefetch/base_prefetcher.hh"
-#include "sim/eventq.hh" // for Event declaration.
 #include "mem/request.hh"
 
 /**
@@ -46,28 +44,11 @@
 void
 BlockingBuffer::regStats(const std::string &name)
 {
-    using namespace Stats;
-    writebacks
-        .init(maxThreadsPerCPU)
-        .name(name + ".writebacks")
-        .desc("number of writebacks")
-        .flags(total)
-        ;
+    MissBuffer::regStats(name);
 }
 
-void
-BlockingBuffer::setCache(BaseCache *_cache)
-{
-    cache = _cache;
-    blkSize = cache->getBlockSize();
-}
 
 void
-BlockingBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
-{
-    prefetcher = _prefetcher;
-}
-void
 BlockingBuffer::handleMiss(PacketPtr &pkt, int blk_size, Tick time)
 {
     Addr blk_addr = pkt->getAddr() & ~(Addr)(blk_size - 1);
@@ -241,3 +222,23 @@ BlockingBuffer::doWriteback(PacketPtr &pkt)
     cache->setBlocked(Blocked_NoWBBuffers);
     cache->setMasterRequest(Request_WB, curTick);
 }
+
+
+MSHR *
+BlockingBuffer::findMSHR(Addr addr)
+{
+    if (miss.addr == addr && miss.pkt)
+        return &miss;
+    return NULL;
+}
+
+
+bool
+BlockingBuffer::findWrites(Addr addr, std::vector<MSHR*>& writes)
+{
+    if (wb.addr == addr && wb.pkt) {
+        writes.push_back(&wb);
+        return true;
+    }
+    return false;
+}
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index a952c688c..205068a8c 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -39,16 +39,13 @@
 #include <vector>
 
 #include "base/misc.hh" // for fatal()
+#include "mem/cache/miss/miss_buffer.hh"
 #include "mem/cache/miss/mshr.hh"
-#include "base/statistics.hh"
-
-class BaseCache;
-class BasePrefetcher;
 
 /**
  * Miss and writeback storage for a blocking cache.
  */
-class BlockingBuffer
+class BlockingBuffer : public MissBuffer
 {
 protected:
     /** Miss storage. */
@@ -56,38 +53,13 @@ protected:
     /** WB storage. */
     MSHR wb;
 
-    //Params
-
-    /** Allocate on write misses. */
-    const bool writeAllocate;
-
-    /** Pointer to the parent cache. */
-    BaseCache* cache;
-
-    BasePrefetcher* prefetcher;
-
-    /** Block size of the parent cache. */
-    int blkSize;
-
-    // Statistics
-    /**
-     * @addtogroup CacheStatistics
-     * @{
-     */
-    /** Number of blocks written back per thread. */
-    Stats::Vector<> writebacks;
-
-    /**
-     * @}
-     */
-
 public:
     /**
      * Builds and initializes this buffer.
      * @param write_allocate If true, treat write misses the same as reads.
      */
     BlockingBuffer(bool write_allocate)
-        : writeAllocate(write_allocate)
+        : MissBuffer(write_allocate)
     {
     }
 
@@ -98,14 +70,6 @@ public:
     void regStats(const std::string &name);
 
     /**
-     * Called by the parent cache to set the back pointer.
-     * @param _cache A pointer to the parent cache.
-     */
-    void setCache(BaseCache *_cache);
-
-    void setPrefetcher(BasePrefetcher *_prefetcher);
-
-    /**
      * Handle a cache miss properly. Requests the bus and marks the cache as
      * blocked.
      * @param pkt The request that missed in the cache.
@@ -184,12 +148,7 @@ public:
      * @param asid The address space id.
      * @return A pointer to miss if it matches.
      */
-    MSHR* findMSHR(Addr addr)
-    {
-        if (miss.addr == addr && miss.pkt)
-            return &miss;
-        return NULL;
-    }
+    MSHR* findMSHR(Addr addr);
 
     /**
      * Searches for the supplied address in the write buffer.
@@ -198,16 +157,7 @@ public:
      * @param writes List of pointers to the matching writes.
      * @return True if there is a matching write.
      */
-    bool findWrites(Addr addr, std::vector<MSHR*>& writes)
-    {
-        if (wb.addr == addr && wb.pkt) {
-            writes.push_back(&wb);
-            return true;
-        }
-        return false;
-    }
-
-
+    bool findWrites(Addr addr, std::vector<MSHR*>& writes);
 
     /**
      * Perform a writeback of dirty data to the given address.
diff --git a/src/mem/cache/miss/miss_buffer.cc b/src/mem/cache/miss/miss_buffer.cc
new file mode 100644
index 000000000..4d9cd0958
--- /dev/null
+++ b/src/mem/cache/miss/miss_buffer.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Erik Hallnor
+ */
+
+#include "cpu/smt.hh" //for maxThreadsPerCPU
+#include "mem/cache/base_cache.hh"
+#include "mem/cache/miss/miss_buffer.hh"
+#include "mem/cache/prefetch/base_prefetcher.hh"
+
+/**
+ * @todo Move writebacks into shared BaseBuffer class.
+ */
+void
+MissBuffer::regStats(const std::string &name)
+{
+    using namespace Stats;
+    writebacks
+        .init(maxThreadsPerCPU)
+        .name(name + ".writebacks")
+        .desc("number of writebacks")
+        .flags(total)
+        ;
+}
+
+void
+MissBuffer::setCache(BaseCache *_cache)
+{
+    cache = _cache;
+    blkSize = cache->getBlockSize();
+}
+
+void
+MissBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
+{
+    prefetcher = _prefetcher;
+}
diff --git a/src/mem/cache/miss/miss_buffer.hh b/src/mem/cache/miss/miss_buffer.hh
new file mode 100644
index 000000000..3e3080578
--- /dev/null
+++ b/src/mem/cache/miss/miss_buffer.hh
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+/**
+ * @file
+ * MissBuffer declaration.
+ */
+
+#ifndef __MISS_BUFFER_HH__
+#define __MISS_BUFFER_HH__
+
+class BaseCache;
+class BasePrefetcher;
+class MSHR;
+
+/**
+ * Abstract base class for cache miss buffering.
+ */
+class MissBuffer
+{
+  protected:
+    /** True if the cache should allocate on a write miss. */
+    const bool writeAllocate;
+
+    /** Pointer to the parent cache. */
+    BaseCache *cache;
+
+    /** The Prefetcher */
+    BasePrefetcher *prefetcher;
+
+    /** Block size of the parent cache. */
+    int blkSize;
+
+    // Statistics
+    /**
+     * @addtogroup CacheStatistics
+     * @{
+     */
+    /** Number of blocks written back per thread. */
+    Stats::Vector<> writebacks;
+
+    /**
+     * @}
+     */
+
+  public:
+    MissBuffer(bool write_allocate)
+        : writeAllocate(write_allocate)
+    {
+    }
+
+    virtual ~MissBuffer() {}
+
+    /**
+     * Called by the parent cache to set the back pointer.
+     * @param _cache A pointer to the parent cache.
+     */
+    void setCache(BaseCache *_cache);
+
+    void setPrefetcher(BasePrefetcher *_prefetcher);
+
+    /**
+     * Register statistics for this object.
+     * @param name The name of the parent cache.
+     */
+    virtual void regStats(const std::string &name);
+
+    /**
+     * Handle a cache miss properly. Either allocate an MSHR for the request,
+     * or forward it through the write buffer.
+     * @param pkt The request that missed in the cache.
+     * @param blk_size The block size of the cache.
+     * @param time The time the miss is detected.
+     */
+    virtual void handleMiss(PacketPtr &pkt, int blk_size, Tick time) = 0;
+
+    /**
+     * Fetch the block for the given address and buffer the given target.
+     * @param addr The address to fetch.
+     * @param asid The address space of the address.
+     * @param blk_size The block size of the cache.
+     * @param time The time the miss is detected.
+     * @param target The target for the fetch.
+     */
+    virtual MSHR *fetchBlock(Addr addr, int blk_size, Tick time,
+                             PacketPtr &target) = 0;
+
+    /**
+     * Selects a outstanding request to service.
+     * @return The request to service, NULL if none found.
+     */
+    virtual PacketPtr getPacket() = 0;
+
+    /**
+     * Set the command to the given bus command.
+     * @param pkt The request to update.
+     * @param cmd The bus command to use.
+     */
+    virtual void setBusCmd(PacketPtr &pkt, Packet::Command cmd) = 0;
+
+    /**
+     * Restore the original command in case of a bus transmission error.
+     * @param pkt The request to reset.
+     */
+    virtual void restoreOrigCmd(PacketPtr &pkt) = 0;
+
+    /**
+     * Marks a request as in service (sent on the bus). This can have side
+     * effect since storage for no response commands is deallocated once they
+     * are successfully sent.
+     * @param pkt The request that was sent on the bus.
+     */
+    virtual void markInService(PacketPtr &pkt, MSHR* mshr) = 0;
+
+    /**
+     * Collect statistics and free resources of a satisfied request.
+     * @param pkt The request that has been satisfied.
+     * @param time The time when the request is satisfied.
+     */
+    virtual void handleResponse(PacketPtr &pkt, Tick time) = 0;
+
+    /**
+     * Removes all outstanding requests for a given thread number. If a request
+     * has been sent to the bus, this function removes all of its targets.
+     * @param threadNum The thread number of the requests to squash.
+     */
+    virtual void squash(int threadNum) = 0;
+
+    /**
+     * Return the current number of outstanding misses.
+     * @return the number of outstanding misses.
+     */
+    virtual int getMisses() = 0;
+
+    /**
+     * Searches for the supplied address in the miss queue.
+     * @param addr The address to look for.
+     * @param asid The address space id.
+     * @return The MSHR that contains the address, NULL if not found.
+     * @warning Currently only searches the miss queue. If non write allocate
+     * might need to search the write buffer for coherence.
+     */
+    virtual MSHR* findMSHR(Addr addr) = 0;
+
+    /**
+     * Searches for the supplied address in the write buffer.
+     * @param addr The address to look for.
+     * @param asid The address space id.
+     * @param writes The list of writes that match the address.
+     * @return True if any writes are found
+     */
+    virtual bool findWrites(Addr addr, std::vector<MSHR*>& writes) = 0;
+
+    /**
+     * Perform a writeback of dirty data to the given address.
+     * @param addr The address to write to.
+     * @param asid The address space id.
+     * @param xc The execution context of the address space.
+     * @param size The number of bytes to write.
+     * @param data The data to write, can be NULL.
+     * @param compressed True if the data is compressed.
+     */
+    virtual void doWriteback(Addr addr, int size, uint8_t *data,
+                             bool compressed) = 0;
+
+    /**
+     * Perform the given writeback request.
+     * @param pkt The writeback request.
+     */
+    virtual void doWriteback(PacketPtr &pkt) = 0;
+
+    /**
+     * Returns true if there are outstanding requests.
+     * @return True if there are outstanding requests.
+     */
+    virtual bool havePending() = 0;
+
+    /**
+     * Add a target to the given MSHR. This assumes it is in the miss queue.
+     * @param mshr The mshr to add a target to.
+     * @param pkt The target to add.
+     */
+    virtual void addTarget(MSHR *mshr, PacketPtr &pkt) = 0;
+
+    /**
+     * Allocate a MSHR to hold a list of targets to a block involved in a copy.
+     * If the block is marked done then the MSHR already holds the data to
+     * fill the block. Otherwise the block needs to be fetched.
+     * @param addr The address to buffer.
+     * @param asid The address space ID.
+     * @return A pointer to the allocated MSHR.
+     */
+    virtual MSHR* allocateTargetList(Addr addr) = 0;
+};
+
+#endif //__MISS_BUFFER_HH__
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 3c4586272..1d3e22326 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -48,16 +48,25 @@ using namespace std;
  */
 MissQueue::MissQueue(int numMSHRs, int numTargets, int write_buffers,
                      bool write_allocate, bool prefetch_miss)
-    : mq(numMSHRs, 4), wb(write_buffers,numMSHRs+1000), numMSHR(numMSHRs),
+    : MissBuffer(write_allocate),
+      mq(numMSHRs, 4), wb(write_buffers,numMSHRs+1000), numMSHR(numMSHRs),
       numTarget(numTargets), writeBuffers(write_buffers),
-      writeAllocate(write_allocate), order(0), prefetchMiss(prefetch_miss)
+      order(0), prefetchMiss(prefetch_miss)
 {
     noTargetMSHR = NULL;
 }
 
+
+MissQueue::~MissQueue()
+{
+}
+
+
 void
 MissQueue::regStats(const string &name)
 {
+    MissBuffer::regStats(name);
+
     Request temp_req((Addr) NULL, 4, 0);
     Packet::Command temp_cmd = Packet::ReadReq;
     Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
@@ -65,13 +74,6 @@ MissQueue::regStats(const string &name)
 
     using namespace Stats;
 
-    writebacks
-        .init(maxThreadsPerCPU)
-        .name(name + ".writebacks")
-        .desc("number of writebacks")
-        .flags(total)
-        ;
-
     // MSHR hit statistics
     for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
         Packet::Command cmd = (Packet::Command)access_idx;
@@ -336,18 +338,6 @@ MissQueue::regStats(const string &name)
 
 }
 
-void
-MissQueue::setCache(BaseCache *_cache)
-{
-    cache = _cache;
-    blkSize = cache->getBlockSize();
-}
-
-void
-MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
-{
-    prefetcher = _prefetcher;
-}
 
 MSHR*
 MissQueue::allocateMiss(PacketPtr &pkt, int size, Tick time)
@@ -706,13 +696,13 @@ MissQueue::squash(int threadNum)
 }
 
 MSHR*
-MissQueue::findMSHR(Addr addr) const
+MissQueue::findMSHR(Addr addr)
 {
     return mq.findMatch(addr);
 }
 
 bool
-MissQueue::findWrites(Addr addr, vector<MSHR*> &writes) const
+MissQueue::findWrites(Addr addr, vector<MSHR*> &writes)
 {
     return wb.findMatches(addr,writes);
 }
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index b67a896f4..1f9bb1e0c 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -38,19 +38,18 @@
 
 #include <vector>
 
+#include "mem/cache/miss/miss_buffer.hh"
 #include "mem/cache/miss/mshr.hh"
 #include "mem/cache/miss/mshr_queue.hh"
 #include "base/statistics.hh"
 
-class BaseCache;
-class BasePrefetcher;
 /**
  * Manages cache misses and writebacks. Contains MSHRs to store miss data
  * and the writebuffer for writes/writebacks.
  * @todo need to handle data on writes better (encapsulate).
  * @todo need to make replacements/writebacks happen in Cache::access
  */
-class MissQueue
+class MissQueue : public MissBuffer
 {
   protected:
     /** The MSHRs. */
@@ -66,16 +65,6 @@ class MissQueue
     const int numTarget;
     /** The number of write buffers. */
     const int writeBuffers;
-    /** True if the cache should allocate on a write miss. */
-    const bool writeAllocate;
-    /** Pointer to the parent cache. */
-    BaseCache* cache;
-
-    /** The Prefetcher */
-    BasePrefetcher *prefetcher;
-
-    /** The block size of the parent cache. */
-    int blkSize;
 
     /** Increasing order number assigned to each incoming request. */
     uint64_t order;
@@ -87,9 +76,6 @@ class MissQueue
      * @addtogroup CacheStatistics
      * @{
      */
-    /** Number of blocks written back per thread. */
-    Stats::Vector<> writebacks;
-
     /** Number of misses that hit in the MSHRs per command and thread. */
     Stats::Vector<> mshr_hits[NUM_MEM_CMDS];
     /** Demand misses that hit in the MSHRs. */
@@ -204,14 +190,6 @@ class MissQueue
     void regStats(const std::string &name);
 
     /**
-     * Called by the parent cache to set the back pointer.
-     * @param _cache A pointer to the parent cache.
-     */
-    void setCache(BaseCache *_cache);
-
-    void setPrefetcher(BasePrefetcher *_prefetcher);
-
-    /**
      * Handle a cache miss properly. Either allocate an MSHR for the request,
      * or forward it through the write buffer.
      * @param pkt The request that missed in the cache.
@@ -289,7 +267,7 @@ class MissQueue
      * @warning Currently only searches the miss queue. If non write allocate
      * might need to search the write buffer for coherence.
      */
-    MSHR* findMSHR(Addr addr) const;
+    MSHR* findMSHR(Addr addr);
 
     /**
      * Searches for the supplied address in the write buffer.
@@ -298,7 +276,7 @@ class MissQueue
      * @param writes The list of writes that match the address.
      * @return True if any writes are found
      */
-    bool findWrites(Addr addr, std::vector<MSHR*>& writes) const;
+    bool findWrites(Addr addr, std::vector<MSHR*>& writes);
 
     /**
      * Perform a writeback of dirty data to the given address.