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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:41:43 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:41:43 -0400 |
| commit | 540e59fd7088fef6cc564babf8c728487b82afd5 (patch) | |
| tree | ce90cac12b6b8087fc5480851138dba13e26e655 /src/mem/cache/mshr.cc | |
| parent | 0c89c15b23d4db50eb08f8ebf2a40b569f41dd29 (diff) | |
| download | gem5-540e59fd7088fef6cc564babf8c728487b82afd5.tar.xz | |
mem: Remove unused RequestCause in cache
This patch removes the RequestCause, and also simplifies how we
schedule the sending of packets through the memory-side port. The
deassertion of bus requests is removed as it is not used.
Diffstat (limited to 'src/mem/cache/mshr.cc')
0 files changed, 0 insertions, 0 deletions