diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-16 15:25:57 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-16 15:25:57 -0700 |
commit | f24ae2ec2a43a5197934668b6f9638ed118994d8 (patch) | |
tree | f51c948e2eedae7d6772228ddb2653aa71622674 /src/mem/cache/mshr.cc | |
parent | 57f2b7db11c9a16f3104588c137e6246bd124041 (diff) | |
download | gem5-f24ae2ec2a43a5197934668b6f9638ed118994d8.tar.xz |
cache: fail store conditionals when upgrade loses race
Requires new "SCUpgradeReq" message that marks upgrades
for store conditionals, so downstream caches can fail
these when they run into invalidations.
See http://www.m5sim.org/flyspray/task/197
Diffstat (limited to 'src/mem/cache/mshr.cc')
-rw-r--r-- | src/mem/cache/mshr.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc index 100e6126a..6333191a4 100644 --- a/src/mem/cache/mshr.cc +++ b/src/mem/cache/mshr.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2002-2005 The Regents of The University of Michigan + * Copyright (c) 2010 Advancec Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -71,7 +72,7 @@ MSHR::TargetList::add(PacketPtr pkt, Tick readyTime, needsExclusive = true; } - if (pkt->cmd == MemCmd::UpgradeReq) { + if (pkt->isUpgrade()) { hasUpgrade = true; } } @@ -99,6 +100,9 @@ MSHR::TargetList::replaceUpgrades() if (i->pkt->cmd == MemCmd::UpgradeReq) { i->pkt->cmd = MemCmd::ReadExReq; DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); + } else if (i->pkt->cmd == MemCmd::SCUpgradeReq) { + i->pkt->cmd = MemCmd::SCUpgradeFailReq; + DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); } } |