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author | Djordje Kovacevic <djordje.kovacevic@arm.com> | 2012-09-25 11:49:41 -0500 |
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committer | Djordje Kovacevic <djordje.kovacevic@arm.com> | 2012-09-25 11:49:41 -0500 |
commit | 80a26a3e39874dab7c0b51cd5ce0258039494e30 (patch) | |
tree | 220868cc2d24070052510a648feb85d9898599ea /src/mem/cache/mshr.hh | |
parent | 6fc0094337bc0356c55232c3850fb5fd2dab1f0c (diff) | |
download | gem5-80a26a3e39874dab7c0b51cd5ce0258039494e30.tar.xz |
MEM: Put memory system document into doxygen
Diffstat (limited to 'src/mem/cache/mshr.hh')
-rw-r--r-- | src/mem/cache/mshr.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh index 7920ad717..87e561ac7 100644 --- a/src/mem/cache/mshr.hh +++ b/src/mem/cache/mshr.hh @@ -47,6 +47,7 @@ class MSHRQueue; /** * Miss Status and handling Register. This class keeps all the information * needed to handle a cache miss including a list of target requests. + * @sa \ref gem5MemorySystem "gem5 Memory System" */ class MSHR : public Packet::SenderState, public Printable { |