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author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:41 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:41 -0500 |
commit | 654266f39cd67055d6176d22a46c7d678f6340c4 (patch) | |
tree | 250cf876eca7a4370ecc3a3e3fa6d9ba695f2830 /src/mem/cache/mshr.hh | |
parent | f02a9338c1efaf7680f598a57ff6607e9b11120e (diff) | |
download | gem5-654266f39cd67055d6176d22a46c7d678f6340c4.tar.xz |
mem: Add cache clusivity
This patch adds a parameter to control the cache clusivity, that is if
the cache is mostly inclusive or exclusive. At the moment there is no
intention to support strict policies, and thus the options are: 1)
mostly inclusive, or 2) mostly exclusive.
The choice of policy guides the behaviuor on a cache fill, and a new
helper function, allocOnFill, is created to encapsulate the decision
making process. For the timing mode, the decision is annotated on the
MSHR on sending out the downstream packet, and in atomic we directly
pass the decision to handleFill. We (ab)use the tempBlock in cases
where we are not allocating on fill, leaving the rest of the cache
unaffected. Simple and effective.
This patch also makes it more explicit that multiple caches are
allowed to consider a block writable (this is the case
also before this patch). That is, for a mostly inclusive cache,
multiple caches upstream may also consider the block exclusive. The
caches considering the block writable/exclusive all appear along the
same path to memory, and from a coherency protocol point of view it
works due to the fact that we always snoop upwards in zero time before
querying any downstream cache.
Note that this patch does not introduce clean writebacks. Thus, for
clean lines we are essentially removing a cache level if it is made
mostly exclusive. For example, lines from the read-only L1 instruction
cache or table-walker cache are always clean, and simply get dropped
rather than being passed to the L2. If the L2 is mostly exclusive and
does not allocate on fill it will thus never hold the line. A follow
on patch adds the clean writebacks.
The patch changes the L2 of the O3_ARM_v7a CPU configuration to be
mostly exclusive (and stats are affected accordingly).
Diffstat (limited to 'src/mem/cache/mshr.hh')
-rw-r--r-- | src/mem/cache/mshr.hh | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh index 11ca4db40..45d7628fd 100644 --- a/src/mem/cache/mshr.hh +++ b/src/mem/cache/mshr.hh @@ -161,6 +161,9 @@ class MSHR : public Packet::SenderState, public Printable /** True if the request is just a simple forward from an upper level */ bool isForward; + /** Keep track of whether we should allocate on fill or not */ + bool allocOnFill; + /** The pending* and post* flags are only valid if inService is * true. Using the accessor functions lets us detect if these * flags are accessed improperly. @@ -218,9 +221,10 @@ class MSHR : public Packet::SenderState, public Printable * @param pkt The original miss. * @param when_ready When should the MSHR be ready to act upon. * @param _order The logical order of this MSHR + * @param alloc_on_fill Should the cache allocate a block on fill */ void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, - Tick when_ready, Counter _order); + Tick when_ready, Counter _order, bool alloc_on_fill); bool markInService(bool pending_dirty_resp); @@ -235,7 +239,8 @@ class MSHR : public Packet::SenderState, public Printable * Add a request to the list of targets. * @param target The target. */ - void allocateTarget(PacketPtr target, Tick when, Counter order); + void allocateTarget(PacketPtr target, Tick when, Counter order, + bool alloc_on_fill); bool handleSnoop(PacketPtr target, Counter order); /** A simple constructor. */ |