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authorSteve Reinhardt <steve.reinhardt@amd.com>2009-02-16 08:56:40 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2009-02-16 08:56:40 -0800
commit89a7fb03934b3e38c7d8b2c4818794b3ec874fdf (patch)
tree53a9b0877112908b1f6c3e5cad256a9b63a5de16 /src/mem/cache/mshr.hh
parent6923282fb5a9ba6af14d19be094839eefe1c34be (diff)
downloadgem5-89a7fb03934b3e38c7d8b2c4818794b3ec874fdf.tar.xz
Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too.
Diffstat (limited to 'src/mem/cache/mshr.hh')
-rw-r--r--src/mem/cache/mshr.hh19
1 files changed, 12 insertions, 7 deletions
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 2ff1c2489..bed7012b0 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -55,20 +55,25 @@ class MSHR : public Packet::SenderState, public Printable
class Target {
public:
+
+ enum Source {
+ FromCPU,
+ FromSnoop,
+ FromPrefetcher
+ };
+
Tick recvTime; //!< Time when request was received (for stats)
Tick readyTime; //!< Time when request is ready to be serviced
Counter order; //!< Global order (for memory consistency mgmt)
PacketPtr pkt; //!< Pending request packet.
- bool cpuSide; //!< Did request come from cpu side or mem side?
+ Source source; //!< Did request come from cpu, memory, or prefetcher?
bool markedPending; //!< Did we mark upstream MSHR
//!< as downstreamPending?
- bool isCpuSide() const { return cpuSide; }
-
Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
- bool _cpuSide, bool _markedPending)
+ Source _source, bool _markedPending)
: recvTime(curTick), readyTime(_readyTime), order(_order),
- pkt(_pkt), cpuSide(_cpuSide), markedPending(_markedPending)
+ pkt(_pkt), source(_source), markedPending(_markedPending)
{}
};
@@ -85,7 +90,7 @@ class MSHR : public Packet::SenderState, public Printable
void resetFlags() { needsExclusive = hasUpgrade = false; }
bool isReset() { return !needsExclusive && !hasUpgrade; }
void add(PacketPtr pkt, Tick readyTime, Counter order,
- bool cpuSide, bool markPending);
+ Target::Source source, bool markPending);
void replaceUpgrades();
void clearDownstreamPending();
bool checkFunctional(PacketPtr pkt);
@@ -238,7 +243,7 @@ public:
if (getNumTargets() != 1)
return false;
Target *tgt = getTarget();
- return tgt->isCpuSide() && !tgt->pkt->needsResponse();
+ return tgt->source == Target::FromCPU && !tgt->pkt->needsResponse();
}
bool promoteDeferredTargets();