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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-16 15:25:57 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-16 15:25:57 -0700 |
| commit | 57f2b7db11c9a16f3104588c137e6246bd124041 (patch) | |
| tree | da67f375e76ebbda46b5528d7c2398efebca1307 /src/mem/cache/mshr_queue.cc | |
| parent | f90319d3b850e6bb773b3bf8548508529970aea2 (diff) | |
| download | gem5-57f2b7db11c9a16f3104588c137e6246bd124041.tar.xz | |
cache: fix dirty bit setting
Only set the dirty bit when we actually write to a block
(not if we thought we might but didn't, as in a failed
SC or CAS). This requires makeing sure the dirty bit
stays set when we get an exclusive (writable) copy
in a cache-to-cache transfer from another owner, which
n turn requires copying the mem-inhibit flag from
timing-mode requests to their associated responses.
Diffstat (limited to 'src/mem/cache/mshr_queue.cc')
0 files changed, 0 insertions, 0 deletions