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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:18 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:18 -0400 |
| commit | 71aca6d29e686ecdec2828c8be1989f74d9b28d3 (patch) | |
| tree | 1ff5b36c08f5e1c3853208674608d141e2924c57 /src/mem/cache/mshr_queue.cc | |
| parent | 7c4dc4491a6367888154129d2799b5f564ecb0d9 (diff) | |
| download | gem5-71aca6d29e686ecdec2828c8be1989f74d9b28d3.tar.xz | |
cache: coherence protocol enhancements & bug fixes
Allow lower-level caches (e.g., L2 or L3) to pass exclusive
copies to higher levels (e.g., L1). This eliminates a lot
of unnecessary upgrade transactions on read-write sequences
to non-shared data.
Also some cleanup of MSHR coherence handling and multiple
bug fixes.
Diffstat (limited to 'src/mem/cache/mshr_queue.cc')
| -rw-r--r-- | src/mem/cache/mshr_queue.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc index b5c6cc7b8..b412891d9 100644 --- a/src/mem/cache/mshr_queue.cc +++ b/src/mem/cache/mshr_queue.cc @@ -197,9 +197,9 @@ MSHRQueue::moveToFront(MSHR *mshr) } void -MSHRQueue::markInService(MSHR *mshr) +MSHRQueue::markInService(MSHR *mshr, PacketPtr pkt) { - if (mshr->markInService()) { + if (mshr->markInService(pkt)) { deallocate(mshr); } else { readyList.erase(mshr->readyIter); |