diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-04-12 09:10:13 -0500 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2019-05-20 13:06:00 +0000 |
commit | b4c472945a6313e1ae1f4ba01477360c372dea6b (patch) | |
tree | 50301b52f72f4a79e9e28b48b2a3fd1fe12ee076 /src/mem/cache/prefetch/Prefetcher.py | |
parent | 526a2fb619f5e5c2c2a7f19498a737571df189b7 (diff) | |
download | gem5-b4c472945a6313e1ae1f4ba01477360c372dea6b.tar.xz |
mem-cache: Add multi-prefetcher adaptor
This patch adds a meta-prefetcher that enables gem5's cache models to
connect to multiple prefetchers. Sub-prefetchers still use the
probes-based interface and training can be controlled
independently. However, when the cache requests a prefetch packet, the
adaptor traverses the priority list of prefetchers and uses the first
prefetcher that is able to generate a prefetch.
Kudos to Mitch Hayenga for the original version of this patch.
Change-Id: I25569a834997e5404c7183ec995d212912c5dcdf
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18868
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/mem/cache/prefetch/Prefetcher.py')
-rw-r--r-- | src/mem/cache/prefetch/Prefetcher.py | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index b933b4953..3810b6afd 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012, 2014 ARM Limited +# Copyright (c) 2012, 2014, 2019 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -99,6 +99,13 @@ class BasePrefetcher(ClockedObject): raise TypeError("probeNames must have at least one element") self.addEvent(HWPProbeEvent(self, simObj, *probeNames)) +class MultiPrefetcher(BasePrefetcher): + type = 'MultiPrefetcher' + cxx_class = 'MultiPrefetcher' + cxx_header = 'mem/cache/prefetch/multi.hh' + + prefetchers = VectorParam.BasePrefetcher([], "Array of prefetchers") + class QueuedPrefetcher(BasePrefetcher): type = "QueuedPrefetcher" abstract = True |