diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/mem/cache/prefetch/Prefetcher.py | |
parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/mem/cache/prefetch/Prefetcher.py')
-rw-r--r-- | src/mem/cache/prefetch/Prefetcher.py | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index c2c17fa96..fa926e235 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -1,5 +1,7 @@ from m5.SimObject import SimObject from m5.params import * +from m5.proxy import * + class BasePrefetcher(SimObject): type = 'BasePrefetcher' abstract = True @@ -13,10 +15,11 @@ class BasePrefetcher(SimObject): "Degree of the prefetch depth") latency = Param.Latency('10t', "Latency of the prefetcher") - use_cpu_id = Param.Bool(True, - "Use the CPU ID to separate calculations of prefetches") + use_master_id = Param.Bool(True, + "Use the master id to separate calculations of prefetches") data_accesses_only = Param.Bool(False, "Only prefetch on data not on instruction accesses") + sys = Param.System(Parent.any, "System this device belongs to") class GHBPrefetcher(BasePrefetcher): type = 'GHBPrefetcher' |