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| author | Mitch Hayenga <mitch.hayenga+gem5@gmail.com> | 2014-01-29 23:21:26 -0600 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga+gem5@gmail.com> | 2014-01-29 23:21:26 -0600 |
| commit | 771c864bf407b57bf91896f38e989e8a36cd9cd1 (patch) | |
| tree | cc0f63f933915a9e58ec2420535c67667af5a180 /src/mem/cache/prefetch/Prefetcher.py | |
| parent | 95735e10e7ea85320ee39c15a4132eece8417af4 (diff) | |
| download | gem5-771c864bf407b57bf91896f38e989e8a36cd9cd1.tar.xz | |
mem: Allowed tagged instruction prefetching in stride prefetcher
For systems with a tightly coupled L2, a stride-based prefetcher may observe
access requests from both instruction and data L1 caches. However, the PC
address of an instruction miss gives no relevant training information to the
stride based prefetcher(there is no stride to train). In theses cases, its
better if the L2 stride prefetcher simply reverted back to a simple N-block
ahead prefetcher. This patch enables this option.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem/cache/prefetch/Prefetcher.py')
| -rw-r--r-- | src/mem/cache/prefetch/Prefetcher.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index 7d7aeed32..c4b6b8845 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -65,6 +65,8 @@ class BasePrefetcher(ClockedObject): "Only prefetch on read requests (write requests ignored)") on_prefetch = Param.Bool(True, "Let lower cache prefetcher train on prefetch requests") + inst_tagged = Param.Bool(True, + "Perform a tagged prefetch for instruction fetches always") sys = Param.System(Parent.any, "System this device belongs to") class GHBPrefetcher(BasePrefetcher): |