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authorMrinmoy Ghosh <mrinmoy.ghosh@arm.com>2012-02-12 16:07:38 -0600
committerMrinmoy Ghosh <mrinmoy.ghosh@arm.com>2012-02-12 16:07:38 -0600
commit7e104a1af235823e3d641a972ea920937f7ec67d (patch)
treed109d98f09652ed11b08dfe0d93a531b28d14df7 /src/mem/cache/prefetch/Prefetcher.py
parentb7cf64398f16e93f118060bd49313f1d37f0e324 (diff)
downloadgem5-7e104a1af235823e3d641a972ea920937f7ec67d.tar.xz
prefetcher: Make prefetcher a sim object instead of it being a parameter on cache
Diffstat (limited to 'src/mem/cache/prefetch/Prefetcher.py')
-rw-r--r--src/mem/cache/prefetch/Prefetcher.py35
1 files changed, 35 insertions, 0 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
new file mode 100644
index 000000000..c2c17fa96
--- /dev/null
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -0,0 +1,35 @@
+from m5.SimObject import SimObject
+from m5.params import *
+class BasePrefetcher(SimObject):
+ type = 'BasePrefetcher'
+ abstract = True
+ size = Param.Int(100,
+ "Number of entries in the hardware prefetch queue")
+ cross_pages = Param.Bool(False,
+ "Allow prefetches to cross virtual page boundaries")
+ serial_squash = Param.Bool(False,
+ "Squash prefetches with a later time on a subsequent miss")
+ degree = Param.Int(1,
+ "Degree of the prefetch depth")
+ latency = Param.Latency('10t',
+ "Latency of the prefetcher")
+ use_cpu_id = Param.Bool(True,
+ "Use the CPU ID to separate calculations of prefetches")
+ data_accesses_only = Param.Bool(False,
+ "Only prefetch on data not on instruction accesses")
+
+class GHBPrefetcher(BasePrefetcher):
+ type = 'GHBPrefetcher'
+ cxx_class = 'GHBPrefetcher'
+
+class StridePrefetcher(BasePrefetcher):
+ type = 'StridePrefetcher'
+ cxx_class = 'StridePrefetcher'
+
+class TaggedPrefetcher(BasePrefetcher):
+ type = 'TaggedPrefetcher'
+ cxx_class = 'TaggedPrefetcher'
+
+
+
+