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authorMitch Hayenga <mitch.hayenga@arm.com>2014-12-23 09:31:18 -0500
committerMitch Hayenga <mitch.hayenga@arm.com>2014-12-23 09:31:18 -0500
commitdf82a2d00311b96ec7fefc901232ba01bbf26d39 (patch)
treeef7d4ac6cc316d9a67eada5df423d32cef97173d /src/mem/cache/prefetch/SConscript
parent6cb58b2bd2ffd19a667e3b9473ff4a0ccfd14c81 (diff)
downloadgem5-df82a2d00311b96ec7fefc901232ba01bbf26d39.tar.xz
mem: Rework the structuring of the prefetchers
Re-organizes the prefetcher class structure. Previously the BasePrefetcher forced multiple assumptions on the prefetchers that inherited from it. This patch makes the BasePrefetcher class truly representative of base functionality. For example, the base class no longer enforces FIFO order. Instead, prefetchers with FIFO requests (like the existing stride and tagged prefetchers) now inherit from a new QueuedPrefetcher base class. Finally, the stride-based prefetcher now assumes a custimizable lookup table (sets/ways) rather than the previous fully associative structure.
Diffstat (limited to 'src/mem/cache/prefetch/SConscript')
-rw-r--r--src/mem/cache/prefetch/SConscript1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript
index cbb6c7a7a..2665d1890 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -33,6 +33,7 @@ Import('*')
SimObject('Prefetcher.py')
Source('base.cc')
+Source('queued.cc')
Source('stride.cc')
Source('tagged.cc')