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authorCurtis Dunham <Curtis.Dunham@arm.com>2014-12-23 09:31:19 -0500
committerCurtis Dunham <Curtis.Dunham@arm.com>2014-12-23 09:31:19 -0500
commit516e6046aefd486768d03ba9c58db80e5ad3fff0 (patch)
tree8fdff59ed87f96003334e63dc95e54f7b75dd21c /src/mem/cache/prefetch/base.cc
parentbd4f901c778e9e3180a60b71a5680eb6724fd637 (diff)
downloadgem5-516e6046aefd486768d03ba9c58db80e5ad3fff0.tar.xz
mem: Hide WriteInvalidate requests from prefetchers
Without this tweak, a prefetcher will happily prefetch data that will promptly be invalidated and overwritten by a WriteInvalidate.
Diffstat (limited to 'src/mem/cache/prefetch/base.cc')
-rw-r--r--src/mem/cache/prefetch/base.cc4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 119397bb5..3ab2d76a6 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -83,7 +83,8 @@ BasePrefetcher::observeAccess(const PacketPtr &pkt) const
{
Addr addr = pkt->getAddr();
bool fetch = pkt->req->isInstFetch();
- bool read= pkt->isRead();
+ bool read = pkt->isRead();
+ bool inv = pkt->isInvalidate();
bool is_secure = pkt->isSecure();
if (pkt->req->isUncacheable()) return false;
@@ -91,6 +92,7 @@ BasePrefetcher::observeAccess(const PacketPtr &pkt) const
if (!fetch && !onData) return false;
if (!fetch && read && !onRead) return false;
if (!fetch && !read && !onWrite) return false;
+ if (!fetch && !read && inv) return false;
if (onMiss) {
return !inCache(addr, is_secure) &&