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author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/mem/cache/prefetch/base.cc | |
parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/mem/cache/prefetch/base.cc')
-rw-r--r-- | src/mem/cache/prefetch/base.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc index 834787db6..467550823 100644 --- a/src/mem/cache/prefetch/base.cc +++ b/src/mem/cache/prefetch/base.cc @@ -42,11 +42,13 @@ #include "mem/cache/prefetch/base.hh" #include "mem/cache/base.hh" #include "mem/request.hh" +#include "sim/system.hh" BasePrefetcher::BasePrefetcher(const Params *p) : SimObject(p), size(p->size), latency(p->latency), degree(p->degree), - useContextId(p->use_cpu_id), pageStop(!p->cross_pages), - serialSquash(p->serial_squash), onlyData(p->data_accesses_only) + useMasterId(p->use_master_id), pageStop(!p->cross_pages), + serialSquash(p->serial_squash), onlyData(p->data_accesses_only), + system(p->sys), masterId(system->getMasterId(name())) { } @@ -230,7 +232,7 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick time) } // create a prefetch memreq - Request *prefetchReq = new Request(*addrIter, blkSize, 0); + Request *prefetchReq = new Request(*addrIter, blkSize, 0, masterId); PacketPtr prefetch = new Packet(prefetchReq, MemCmd::HardPFReq, Packet::Broadcast); prefetch->allocate(); |