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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-12-23 09:31:18 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-12-23 09:31:18 -0500 |
| commit | bd4f901c778e9e3180a60b71a5680eb6724fd637 (patch) | |
| tree | 059ddcc960962d505bf7ab95c9c52093ba0c05e3 /src/mem/cache/prefetch/base.cc | |
| parent | 4acd4a205525a79555f783767ab0d6a5f9c31eb5 (diff) | |
| download | gem5-bd4f901c778e9e3180a60b71a5680eb6724fd637.tar.xz | |
mem: Fix event scheduling issue for prefetches
The cache's MemSidePacketQueue schedules a sendEvent based upon
nextMSHRReadyTime() which is the time when the next MSHR is ready or whenever
a future prefetch is ready. However, a prefetch being ready does not guarentee
that it can obtain an MSHR. So, when all MSHRs are full,
the simulation ends up unnecessiciarly scheduling a sendEvent every picosecond
until an MSHR is finally freed and the prefetch can happen.
This patch fixes this by not signaling the prefetch ready time if the prefetch
could not be generated. The event is rescheduled as soon as a MSHR becomes
available.
Diffstat (limited to 'src/mem/cache/prefetch/base.cc')
0 files changed, 0 insertions, 0 deletions