mem-cache: implement a probe-based interface

The HW Prefetcher of a cache can now listen events
from their associated CPUs and from its own cache.

Change-Id: I28aecd8faf8ed44be94464d84485bd1cea2efae3
Reviewed-on: https://gem5-review.googlesource.com/c/14155
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

1 files changed, 45 insertions, 2 deletions

diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 22a12ba5f..41c02ac72 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -51,16 +51,24 @@
 #include <cassert>
 
 #include "base/intmath.hh"
+#include "cpu/base.hh"
 #include "mem/cache/base.hh"
 #include "params/BasePrefetcher.hh"
 #include "sim/system.hh"
 
+void
+BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
+{
+    parent.probeNotify(pkt);
+}
+
 BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
-    : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
+    : ClockedObject(p), listeners(), cache(nullptr), blkSize(0), lBlkSize(0),
       system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
       onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
       masterId(system->getMasterId(this)),
-      pageBytes(system->getPageBytes())
+      pageBytes(system->getPageBytes()),
+      prefetchOnAccess(p->prefetch_on_access)
 {
 }
 
@@ -163,3 +171,38 @@ BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
 {
     return page + (blockIndex << lBlkSize);
 }
+
+void
+BasePrefetcher::probeNotify(const PacketPtr &pkt)
+{
+    // Don't notify prefetcher on SWPrefetch, cache maintenance
+    // operations or for writes that we are coaslescing.
+    if (pkt->cmd.isSWPrefetch()) return;
+    if (pkt->req->isCacheMaintenance()) return;
+    if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
+    notify(pkt);
+}
+
+void
+BasePrefetcher::regProbeListeners()
+{
+    /**
+     * If no probes were added by the configuration scripts, connect to the
+     * parent cache using the probe "Miss". Also connect to "Hit", if the
+     * cache is configured to prefetch on accesses.
+     */
+    if (listeners.empty() && cache != nullptr) {
+        ProbeManager *pm(cache->getProbeManager());
+        listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
+        if (prefetchOnAccess) {
+            listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
+        }
+    }
+}
+
+void
+BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
+{
+    ProbeManager *pm(obj->getProbeManager());
+    listeners.push_back(new PrefetchListener(*this, pm, name));
+}